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[CIR] Lower cir.bool to i1 #1158

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merged 2 commits into from
Jan 6, 2025
Merged

[CIR] Lower cir.bool to i1 #1158

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db8fde4
[CIR][ThroughMLIR] Lower `cir.bool` to i1
orbiri Nov 23, 2024
3450f9e
[CIR][DirectToLLVM] Lower `cir.bool` to i1
orbiri Dec 21, 2024
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2 changes: 1 addition & 1 deletion clang/lib/CIR/CodeGen/CIRGenModule.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -820,7 +820,7 @@ void CIRGenModule::replaceGlobal(cir::GlobalOp Old, cir::GlobalOp New) {
mlir::Type ptrTy = builder.getPointerTo(OldTy);
mlir::Value cast =
builder.createBitcast(GGO->getLoc(), UseOpResultValue, ptrTy);
UseOpResultValue.replaceAllUsesExcept(cast, {cast.getDefiningOp()});
UseOpResultValue.replaceAllUsesExcept(cast, cast.getDefiningOp());
}
}
}
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297 changes: 190 additions & 107 deletions clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
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54 changes: 45 additions & 9 deletions clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
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Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,18 @@
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
#include "mlir/IR/MLIRContext.h"
#include "mlir/Interfaces/DataLayoutInterfaces.h"
#include "mlir/Transforms/DialectConversion.h"

namespace cir {
namespace direct {

/// Convert a CIR attribute to an LLVM attribute. May use the datalayout for
/// lowering attributes to-be-stored in memory.
mlir::Value lowerCirAttrAsValue(mlir::Operation *parentOp, mlir::Attribute attr,
mlir::ConversionPatternRewriter &rewriter,
const mlir::TypeConverter *converter);
const mlir::TypeConverter *converter,
mlir::DataLayout const &dataLayout);

mlir::LLVM::Linkage convertLinkage(cir::GlobalLinkageKind linkage);

Expand Down Expand Up @@ -137,7 +142,13 @@ class CIRToLLVMMemSetInlineOpLowering

class CIRToLLVMPtrStrideOpLowering
: public mlir::OpConversionPattern<cir::PtrStrideOp> {
mlir::DataLayout const &dataLayout;

public:
CIRToLLVMPtrStrideOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), dataLayout(dataLayout) {}
using mlir::OpConversionPattern<cir::PtrStrideOp>::OpConversionPattern;

mlir::LogicalResult
Expand Down Expand Up @@ -216,9 +227,15 @@ class CIRToLLVMBrCondOpLowering
};

class CIRToLLVMCastOpLowering : public mlir::OpConversionPattern<cir::CastOp> {
mlir::DataLayout const &dataLayout;

mlir::Type convertTy(mlir::Type ty) const;

public:
CIRToLLVMCastOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), dataLayout(dataLayout) {}
using mlir::OpConversionPattern<cir::CastOp>::OpConversionPattern;

mlir::LogicalResult
Expand Down Expand Up @@ -302,12 +319,15 @@ class CIRToLLVMAllocaOpLowering

class CIRToLLVMLoadOpLowering : public mlir::OpConversionPattern<cir::LoadOp> {
cir::LowerModule *lowerMod;
mlir::DataLayout const &dataLayout;

public:
CIRToLLVMLoadOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
cir::LowerModule *lowerModule)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule) {}
cir::LowerModule *lowerModule,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule),
dataLayout(dataLayout) {}

mlir::LogicalResult
matchAndRewrite(cir::LoadOp op, OpAdaptor,
Expand All @@ -317,12 +337,15 @@ class CIRToLLVMLoadOpLowering : public mlir::OpConversionPattern<cir::LoadOp> {
class CIRToLLVMStoreOpLowering
: public mlir::OpConversionPattern<cir::StoreOp> {
cir::LowerModule *lowerMod;
mlir::DataLayout const &dataLayout;

public:
CIRToLLVMStoreOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
cir::LowerModule *lowerModule)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule) {}
cir::LowerModule *lowerModule,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule),
dataLayout(dataLayout) {}

mlir::LogicalResult
matchAndRewrite(cir::StoreOp op, OpAdaptor,
Expand All @@ -332,12 +355,15 @@ class CIRToLLVMStoreOpLowering
class CIRToLLVMConstantOpLowering
: public mlir::OpConversionPattern<cir::ConstantOp> {
cir::LowerModule *lowerMod;
mlir::DataLayout const &dataLayout;

public:
CIRToLLVMConstantOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
cir::LowerModule *lowerModule)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule) {
cir::LowerModule *lowerModule,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule),
dataLayout(dataLayout) {
setHasBoundedRewriteRecursion();
}

Expand Down Expand Up @@ -538,12 +564,15 @@ class CIRToLLVMSwitchFlatOpLowering
class CIRToLLVMGlobalOpLowering
: public mlir::OpConversionPattern<cir::GlobalOp> {
cir::LowerModule *lowerMod;
mlir::DataLayout const &dataLayout;

public:
CIRToLLVMGlobalOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
cir::LowerModule *lowerModule)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule) {
cir::LowerModule *lowerModule,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), lowerMod(lowerModule),
dataLayout(dataLayout) {
setHasBoundedRewriteRecursion();
}

Expand Down Expand Up @@ -904,7 +933,14 @@ class CIRToLLVMTrapOpLowering : public mlir::OpConversionPattern<cir::TrapOp> {

class CIRToLLVMInlineAsmOpLowering
: public mlir::OpConversionPattern<cir::InlineAsmOp> {
mlir::DataLayout const &dataLayout;

public:
CIRToLLVMInlineAsmOpLowering(const mlir::TypeConverter &typeConverter,
mlir::MLIRContext *context,
mlir::DataLayout const &dataLayout)
: OpConversionPattern(typeConverter, context), dataLayout(dataLayout) {}

using mlir::OpConversionPattern<cir::InlineAsmOp>::OpConversionPattern;

mlir::LogicalResult
Expand Down
5 changes: 1 addition & 4 deletions clang/lib/CIR/Lowering/ThroughMLIR/LowerCIRLoopToSCF.cpp
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Expand Up @@ -337,11 +337,8 @@ class CIRConditionOpLowering
auto *parentOp = op->getParentOp();
return llvm::TypeSwitch<mlir::Operation *, mlir::LogicalResult>(parentOp)
.Case<mlir::scf::WhileOp>([&](auto) {
auto condition = adaptor.getCondition();
auto i1Condition = rewriter.create<mlir::arith::TruncIOp>(
op.getLoc(), rewriter.getI1Type(), condition);
rewriter.replaceOpWithNewOp<mlir::scf::ConditionOp>(
op, i1Condition, parentOp->getOperands());
op, adaptor.getCondition(), parentOp->getOperands());
return mlir::success();
})
.Default([](auto) { return mlir::failure(); });
Expand Down
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