[ImportVerilog] add real literal support, refine real type, and add real format support #8020
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…eal format support
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Maybe we can extend its argument and result type, like |
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Could you add some test cases? And thanks for your work on this 😄. |
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| let description = [{ | ||
| }]; |
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| let description = [{ | |
| }]; |
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| $value `,` | ||
| attr-dict `:` type($value) |
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| $value `,` | |
| attr-dict `:` type($value) | |
| $value `,` attr-dict `:` type($value) |
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| // The result of using logical or relational operators or the inside operator on real operands shall be a | ||
| // single-bit scalar value. | ||
| // For other operators, if any operand, except before the ? in the conditional operator, is real, the result is | ||
| // real. Otherwise, if any operand, except before the ? in the conditional operator, is shortreal, the result is | ||
| // shortreal. | ||
| if(isa<moore::RealType>(lhsType) || isa<moore::RealType>(rhsType)) { | ||
| if(!isa<moore::RealType>(lhsType)) | ||
| lhs = builder.create<moore::ConversionOp>(lhs.getLoc(), moore::RealType::get(context.getContext()), lhs); | ||
| if(!isa<moore::RealType>(rhsType)) | ||
| rhs = builder.create<moore::ConversionOp>(rhs.getLoc(), moore::RealType::get(context.getContext()), rhs); | ||
| } else if(isa<moore::ShortRealType>(lhsType) || isa<moore::ShortRealType>(rhsType)) { | ||
| if(!isa<moore::ShortRealType>(lhsType)) | ||
| lhs = builder.create<moore::ConversionOp>(lhs.getLoc(), moore::ShortRealType::get(context.getContext()), lhs); | ||
| if(!isa<moore::ShortRealType>(rhsType)) | ||
| rhs = builder.create<moore::ConversionOp>(rhs.getLoc(), moore::ShortRealType::get(context.getContext()), rhs); |
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We need to limit code <= 80 chars.
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This PR is aimed to support systemverilog real, shortreal, realtime, and there conversion and operation.
One thing I'm not so sure about is that
why this opbase just support SimpleBitVectorType? is there any shortcoming to just convert it to a UnpackedType? I also want to use this OpBase support float point operation.