BuildTask: write debug RTLIL.

kivikakk · Jun 6, 2024 · 02f9694 · 02f9694
1 parent 08de64a
commit 02f9694
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala b/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala
@@ -58,11 +58,13 @@ private[chryse] object BuildTask extends BaseTask {
     writePath(verilogPath, verilog)
 
     val yosysScriptPath = s"$buildDir/${platform.id}/$name.ys"
+    val rtlilPath       = s"$buildDir/${platform.id}/$name.il"
     val jsonPath        = s"$buildDir/${platform.id}/$name.json"
     writePath(
       yosysScriptPath,
       s"""read_verilog -sv $verilogPath
          |${platform.yosysSynthCommand("chrysetop")}
+         |write_rtlil $rtlilPath
          |write_json $jsonPath""".stripMargin,
     )