instruction_check: Add Skylake AVX512 cpuid

AVX512F AVX512DQ AVX512BW AVX512CD AVX512VL are introduced by Intel Skylake server platform. Signed-off-by: Xudong Hao <[email protected]>
intel · Jan 15, 2025 · cf5656f · cf5656f
1 parent 64bb081
commit cf5656f
Showing 1 changed file with 20 additions and 0 deletions.
diff --git a/BM/instruction-check/feature_list.py b/BM/instruction-check/feature_list.py
@@ -33,14 +33,34 @@
         "cpuid": ['7', '0', '0', '0', 'b', '15'],
         "platforms": {"SPR", "EMR", "GNR", "SRF", "CWF"}
     },
+    "AVX512_F": {
+        "cpuid": ['7', '0', '0', '0', 'b', '16'],
+        "platforms": {"SPR", "EMR", "GNR"}
+    },
+    "AVX512_DQ": {
+        "cpuid": ['7', '0', '0', '0', 'b', '17'],
+        "platforms": {"SPR", "EMR", "GNR"}
+    },
     "AVX512_IFMA": {
         "cpuid": ['7', '0', '0', '0', 'b', '21'],
         "platforms": {"SPR", "EMR", "GNR"}
     },
+    "AVX512_CD": {
+        "cpuid": ['7', '0', '0', '0', 'b', '28'],
+        "platforms": {"SPR", "EMR", "GNR"}
+    },
     "SHA_NI": {
         "cpuid": ['7', '0', '0', '0', 'b', '29'],
         "platforms": {"SPR", "EMR", "GNR", "SRF", "CWF"}
     },
+    "AVX512_BW": {
+        "cpuid": ['7', '0', '0', '0', 'b', '30'],
+        "platforms": {"SPR", "EMR", "GNR"}
+    },
+    "AVX512_VL": {
+        "cpuid": ['7', '0', '0', '0', 'b', '31'],
+        "platforms": {"SPR", "EMR", "GNR"}
+    },
     "AVX512_VBMI": {
         "cpuid": ['7', '0', '0', '0', 'c', '1'],
         "platforms": {"SPR", "EMR", "GNR"}