rasc for ra4m1_ek

hw/bsp/ra/boards/ra4m1_ek/board.h

@@ -31,21 +31,9 @@
 extern "C" {
 #endif
 
-#define LED1          BSP_IO_PORT_01_PIN_06
-#define LED_STATE_ON  1
-
-#define SW1                   BSP_IO_PORT_01_PIN_05
+#define LED_STATE_ON          1
 #define BUTTON_STATE_ACTIVE   0
 
-static const ioport_pin_cfg_t board_pin_cfg[] = {
-    {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
-    {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
-    // USB FS D+, D-, VBus
-    {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-    {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-    {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-};
-
 #ifdef __cplusplus
 }
 #endif

hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h

@@ -1,35 +1,62 @@
 /* generated configuration header file - do not edit */
 #ifndef BSP_CFG_H_
 #define BSP_CFG_H_
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#undef RA_NOT_DEFINED
-#define BSP_CFG_RTOS (0)
-#if defined(_RA_BOOT_IMAGE)
-#define BSP_CFG_BOOT_IMAGE (1)
-#endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x800)
-#define BSP_CFG_HEAP_BYTES (0x1000)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT     ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE	(0)
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE		(0)
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-
+#ifdef __cplusplus
+            extern "C" {
+            #endif
+
+            #include "bsp_clock_cfg.h"
+            #include "bsp_mcu_family_cfg.h"
+            #include "board_cfg.h"
+            #define RA_NOT_DEFINED 0
+            #ifndef BSP_CFG_RTOS
+             #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (2)
+             #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+              #define BSP_CFG_RTOS (1)
+             #else
+              #define BSP_CFG_RTOS (0)
+             #endif
+            #endif
+            #ifndef BSP_CFG_RTC_USED
+             #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+            #endif
+            #undef RA_NOT_DEFINED
+            #if defined(_RA_BOOT_IMAGE)
+             #define BSP_CFG_BOOT_IMAGE (1)
+            #endif
+            #define BSP_CFG_MCU_VCC_MV (3300)
+            #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+            #define BSP_CFG_HEAP_BYTES (0x1000)
+            #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+            #define BSP_CFG_ASSERT (0)
+            #define BSP_CFG_ERROR_LOG (0)
+
+            #define BSP_CFG_PFS_PROTECT ((1))
+
+            #define BSP_CFG_C_RUNTIME_INIT ((1))
+            #define BSP_CFG_EARLY_INIT     ((0))
+
+            #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+            #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+            #endif
+
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+            #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+            #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+            #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+            #endif
+            #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+            #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+            #endif
+
+            #ifdef __cplusplus
+            }
+            #endif
 #endif /* BSP_CFG_H_ */

hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h

@@ -2,10 +2,10 @@
 #ifndef BSP_MCU_DEVICE_PN_CFG_H_
 #define BSP_MCU_DEVICE_PN_CFG_H_
 #define BSP_MCU_R7FA4M1AB3CFP
-#define BSP_MCU_FEATURE_SET ('A')
-#define BSP_ROM_SIZE_BYTES (262144)
-#define BSP_RAM_SIZE_BYTES (32768)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (100)
+      #define BSP_MCU_FEATURE_SET ('A')
+      #define BSP_ROM_SIZE_BYTES (262144)
+      #define BSP_RAM_SIZE_BYTES (32768)
+      #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+      #define BSP_PACKAGE_LQFP
+      #define BSP_PACKAGE_PINS (100)
 #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h

@@ -1,78 +1,84 @@
-/* generated configuration header file through renesas e2 studio */
+/* generated configuration header file - do not edit */
 #ifndef BSP_MCU_FAMILY_CFG_H_
 #define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+            extern "C" {
+            #endif
 
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-
-#define BSP_MCU_GROUP_RA4M1 (1)
-#define BSP_LOCO_HZ                 (32768)
-#define BSP_MOCO_HZ                 (8000000)
-#define BSP_SUB_CLOCK_HZ            (32768)
-#if   BSP_CFG_HOCO_FREQUENCY == 0
-  #define BSP_HOCO_HZ             (24000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
-  #define BSP_HOCO_HZ             (32000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 4
-  #define BSP_HOCO_HZ             (48000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 5
-  #define BSP_HOCO_HZ             (64000000)
-#else
-  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-#endif
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+            #include "bsp_mcu_device_pn_cfg.h"
+            #include "bsp_mcu_device_cfg.h"
+            #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
+            #include "bsp_clock_cfg.h"
+            #define BSP_MCU_GROUP_RA4M1 (1)
+            #define BSP_LOCO_HZ                 (32768)
+            #define BSP_MOCO_HZ                 (8000000)
+            #define BSP_SUB_CLOCK_HZ            (32768)
+            #if   BSP_CFG_HOCO_FREQUENCY == 0
+                #define BSP_HOCO_HZ             (24000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ             (32000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 4
+                #define BSP_HOCO_HZ             (48000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 5
+                #define BSP_HOCO_HZ             (64000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+            #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+            #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+            #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
 
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
-#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
-#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
-#endif
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+            #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+            #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+            #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+            #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+            #define OFS_SEQ5 (1 << 28) | (1 << 30)
+            #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+            #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+            #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+            #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+            #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+            #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+            #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+            #endif
+            /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+            #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
 
-/*
- ID Code
- Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
- WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
- */
-#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+            /*
+            ID Code
+            Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+            WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+            */
+            #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
             #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
             #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
             #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
             #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
             #else
-/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
-#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
-#endif
+            /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+            #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+            #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+            #endif
 
+            #ifdef __cplusplus
+            }
+            #endif
 #endif /* BSP_MCU_FAMILY_CFG_H_ */

hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h

@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define SW1 (BSP_IO_PORT_01_PIN_05)
+#define LED1 (BSP_IO_PORT_01_PIN_06)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */

hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h

@@ -7,7 +7,7 @@
 #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
 #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
 #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
-#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U,0U) /* PLL Mul x8 */
 #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
 #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */

hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c

@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}

hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h

@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */