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Added STIDC and UTIDC registers #247

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Added STIDC and UTIDC registers #247

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francislaus
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This PR adds the SCRs for supervisor and user thread ID capability registers, which are used in compartmentalisation.

@francislaus francislaus self-assigned this Apr 18, 2024
@francislaus francislaus marked this pull request as ready for review April 26, 2024 09:36
@francislaus francislaus requested a review from qwattash April 26, 2024 09:36
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Looks good to me, I'm not sure why the Morello test is failing though.
Checkpatch complains about // comments but all files uses them, I don't see much of a point to have multiple comment styles here just for that.

@arichardson
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The current spec has UTID as a view of STID (and no MTID at all), do we want to match that instead?

@jrtc27
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jrtc27 commented May 8, 2024

The current spec has UTID as a view of STID (and no MTID at all), do we want to match that instead?

That's being changed, it was a bad idea to not have a separate ID register for S-mode's own use

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Minor suggestion

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One minor comment otherwise lgtm

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Could you rebase and squash? Then we can merge this to dev.

@arichardson arichardson changed the base branch from qemu-cheri to dev February 5, 2025 19:09
@francislaus francislaus force-pushed the faf28_tid branch 2 times, most recently from c5e6c12 to 9d87356 Compare February 6, 2025 11:07
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4 participants