js5005 is a virtual CPU with every logic gate simulted. It is an upgraded version of the i4004 CPU, making it fast and efficient. It has many tweaks and upgrades to allow better writing of code, including a built in register and RAM viewer. It's instruction set makes it versatile, even though it's only 8 bits.
A live version can be found at http://cpu.pepsipu.com/
For some reason, register prefixes are broken. You can still access registers, but instead of doing, for example, "cmp r3 r4", do "cmp 3 4". If you do not, it seems that all registers become r0. I'll implement a fix soon.
the nop instructions is a no-operation instruction. It takes no parameters and does absolutely nothing.
nop
ldm loads an 8 bit number into the accumulator.
ldm <8 bit number>
ld loads the content of the index register into the accumulator.
ld r<index register>
xch swaps the value of the accumulator and the target register.
xch r<index register>
add adds together the accumulator and the content of the index register.
add r<index register>
sub subtracts the accumulator by the content of the index register. The index register should be in two's complement form.
sub r<index register>
inc increments the index register by one.
inc r<index register>
ret sets the instruction pointer to the topmost return pointer on the stack. This is used to return from a subroutine.
ret
jin sets the instruction pointer to the content of the index register.
jin r<index register>
fch takes two registers as input, and will set the second register as a value in RAM, which has it's address decided by the first register's content.
fch r<index register>, r<index register>
jmp sets the instruction pointer to the parameter given.
jmp 0x<hex address>
call pushes the current instruction pointer on the stack, then jumps to a subroutine. After the ret instruction, it will return to the instruction pointer's original location.
call 0x<hex address>
cmp toggle the zero flag if both contents of the index registers are equal. je or jne can be used after this instruction for a conditional jump.
cmp r<index register>, r<index register>
je sets the instruction pointer to the parameter if the zero flag is set.
je 0x<hex address>
jne sets the instruction pointer to the parameter if the zero flag is not set.
jne 0x<hex address>
str stores the value of the second register in the RAM address that is stored in the first register.
str r<index register>, r<index register>
rr rotates the content of the register to the right.
rr r<index register>
rl rotates the content of the register to the left.
rr r<index register>
and does a logical and operation with the content of the two registers and stores the result in second register.
and r<index register>, r<index register>
logical and - and - 19
or does a logical or operation with the content of the two registers and stores the result in second register.
or r<index register>, r<index register>
not inverts the content of the index register.
not r<index register>
xor does a logical exclusive or operation with the content of the two registers and stores the result in second register.
xor r<index register>, r<index register>
dbg pauses program execution and allows the user to browse the ram and view the registers.
dbg
colr sets the color register to the parameter. When scrn is called, this is the color that is used. Keep in mind this is an 8 bit color.
color <8 bit number>
scrn takes two parameters, the x and the y position of the pixel you are coloring. The display is 16 by 16, meaning x and y can be from 0 to 15. The pixel's color comes from the color register, which is set with the colr instruction.
scrn <4 bit number>, <4 bit number>