diff --git a/lib/Conversion/ImportVerilog/Statements.cpp b/lib/Conversion/ImportVerilog/Statements.cpp
index fe1bc80f5d2c..1ae9583277d7 100644
--- a/lib/Conversion/ImportVerilog/Statements.cpp
+++ b/lib/Conversion/ImportVerilog/Statements.cpp
@@ -662,6 +662,21 @@ struct StmtVisitor {
     return false;
   }
 
+  /// Handle procedural assign statements.
+  LogicalResult visit(const slang::ast::ProceduralAssignStatement &stmt) {
+    if (stmt.isForce) {
+      auto loc = context.convertLocation(stmt.sourceRange);
+      mlir::emitError(loc, "force assignments not supported.");
+      return mlir::failure();
+    }
+
+    auto value = context.convertRvalueExpression(stmt.assignment);
+    if (!value)
+      return mlir::failure();
+
+    return mlir::success();
+  }
+
   /// Create the optional diagnostic message print for finish-like ops.
   void createFinishMessage(const slang::ast::Expression *verbosityExpr) {
     unsigned verbosity = 1;
diff --git a/test/Conversion/ImportVerilog/basic.sv b/test/Conversion/ImportVerilog/basic.sv
index 7959351f000c..36f05a6d58c6 100644
--- a/test/Conversion/ImportVerilog/basic.sv
+++ b/test/Conversion/ImportVerilog/basic.sv
@@ -595,6 +595,10 @@ module Statements;
     // CHECK: [[TMP1:%.+]] = moore.read %y
     // CHECK: moore.nonblocking_assign %x, [[TMP1]] : i1
     x <= y;
+
+    // CHECK: [[TMP1:%.+]] = moore.read %y
+    // CHECK: moore.blocking_assign %x, [[TMP1]] : i1
+    assign x = y;
   end
 endmodule