From c5ebbb3b8a744c2b99e3c1974f555cd4d0ebe99d Mon Sep 17 00:00:00 2001
From: Will Dietz <will.dietz@sifive.com>
Date: Wed, 8 Jan 2025 16:31:12 -0600
Subject: [PATCH] firrtl.view: Take operands directly, not probes.

---
 include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td | 4 ++--
 test/Dialect/FIRRTL/round-trip.mlir              | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td b/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
index 9a24d7f2d77d..4d3cf5cdc24c 100644
--- a/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
+++ b/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
@@ -239,8 +239,8 @@ def ViewIntrinsicOp : FIRRTLOp<"view", []> {
     debugging in a waveform.  This is _not_ a true SystemVerilog Interface, it
     is only lowered to one.
   }];
-  let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<RefType>:$probes);
-  let assemblyFormat = "$name `,` $augmentedType (`,` $probes^)? attr-dict `:` type($probes)";
+  let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<FIRRTLBaseType>:$inputs);
+  let assemblyFormat = "$name `,` $augmentedType (`,` $inputs^)? attr-dict `:` type($inputs)";
 }
 
 #endif // CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD
diff --git a/test/Dialect/FIRRTL/round-trip.mlir b/test/Dialect/FIRRTL/round-trip.mlir
index 345792b40148..62d4734b3941 100644
--- a/test/Dialect/FIRRTL/round-trip.mlir
+++ b/test/Dialect/FIRRTL/round-trip.mlir
@@ -41,7 +41,7 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
   %po = firrtl.int.generic "params_and_operand" <X: i64 = 123> %ui1 : (!firrtl.uint<1>) -> !firrtl.clock
   firrtl.int.generic "inputs" %clock, %ui1, %clock : (!firrtl.clock, !firrtl.uint<1>, !firrtl.clock) -> ()
 
-  %probe = firrtl.wire : !firrtl.probe<uint<1>>
+  %val = firrtl.wire : !firrtl.uint<1>
   // CHECK: firrtl.view "View"
   // CHECK-SAME: <{
   // CHECK-SAME:     elements = [
@@ -56,7 +56,7 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
   // CHECK-SAME:         name = "qux"
   // CHECK-SAME:       }
   // CHECK-SAME:     ]
-  // CHECK-SAME: }>, %probe, %probe : !firrtl.probe<uint<1>>, !firrtl.probe<uint<1>>
+  // CHECK-SAME: }>, %val, %val : !firrtl.uint<1>, !firrtl.uint<1>
   firrtl.view "View", <{
     class = "sifive.enterprise.grandcentral.AugmentedBundleType",
     defName = "Bar",
@@ -72,7 +72,7 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
         name = "qux"
       }
     ]
-  }>, %probe, %probe : !firrtl.probe<uint<1>>, !firrtl.probe<uint<1>>
+  }>, %val, %val : !firrtl.uint<1>, !firrtl.uint<1>
 }
 
 // CHECK-LABEL: firrtl.module @FPGAProbe