From 3db7c017b416e5eea657050131b6323463620c8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 22 Jan 2025 12:32:08 +0100 Subject: [PATCH 1/3] targets: efinix_ti375_c529_dev_kit: be able to use ddr memory on all cpus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit be able to use ddr memory on all cpus, including those without a seperate memory bus. Signed-off-by: Fin Maaß --- .../targets/efinix_ti375_c529_dev_kit.py | 24 +++++++++++-------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/litex_boards/targets/efinix_ti375_c529_dev_kit.py b/litex_boards/targets/efinix_ti375_c529_dev_kit.py index aa8ad349d..d9464772a 100755 --- a/litex_boards/targets/efinix_ti375_c529_dev_kit.py +++ b/litex_boards/targets/efinix_ti375_c529_dev_kit.py @@ -649,13 +649,6 @@ def generate(root, namespaces): Subsignal("resetn", Pins(1)), )] - if hasattr(self.cpu, "add_memory_buses"): - self.cpu.add_memory_buses(address_width = 32, data_width = data_width) - - assert len(self.cpu.memory_buses) == 1 - mbus = self.cpu.memory_buses[0] - self.comb +=mbus.connect(axi_bus) - io = platform.add_iface_ios(ios) self.comb += [ io.ar_valid.eq(axi_bus.ar.valid), @@ -719,12 +712,23 @@ def generate(root, namespaces): self.sync += self.cfg_count.eq(self.cfg_count + (self.cfg_count != 0xFF)) self.sync += self.cfg_state.eq(self.cfg_state | (self.cfg_count == 0xFF)) - # Use DRAM's target0 port as Main Ram. - self.bus.add_region("main_ram", SoCRegion( + soc_region = SoCRegion( origin = 0x4000_0000, size = 0x4000_0000, # 1GB. mode ="rwx", - )) + ) + # Use DRAM's target0 port as Main Ram. + if hasattr(self.cpu, "add_memory_buses"): + self.cpu.add_memory_buses(address_width = 32, data_width = data_width) + + assert len(self.cpu.memory_buses) == 1 + mbus = self.cpu.memory_buses[0] + self.comb +=mbus.connect(axi_bus) + self.bus.add_region("main_ram", soc_region) + else: + axi_lite_bus = axi.AXILiteInterface(data_width=data_width, address_width=axi_bus.address_width) + self.submodules += axi.AXILite2AXI(axi_lite_bus, axi_bus) + self.bus.add_slave("main_ram", axi_lite_bus, soc_region) # Build -------------------------------------------------------------------------------------------- From 42a7db0ef390022717d8091befccfbefce58ff79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 22 Jan 2025 12:34:56 +0100 Subject: [PATCH 2/3] targets: efinix_ti375_c529_dev_kit: simplify ddr part MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit simplify ddr part by using ``axi_bus.get_ios()`` and ``axi_bus.connect_to_pads``. Signed-off-by: Fin Maaß --- .../targets/efinix_ti375_c529_dev_kit.py | 233 +++++++----------- 1 file changed, 84 insertions(+), 149 deletions(-) diff --git a/litex_boards/targets/efinix_ti375_c529_dev_kit.py b/litex_boards/targets/efinix_ti375_c529_dev_kit.py index d9464772a..3d1713024 100755 --- a/litex_boards/targets/efinix_ti375_c529_dev_kit.py +++ b/litex_boards/targets/efinix_ti375_c529_dev_kit.py @@ -335,7 +335,7 @@ def __init__(self, import xml.etree.ElementTree as et data_width = 512 - axi_bus = axi.AXIInterface(data_width=data_width, address_width=30, id_width=8) # 256MB. + axi_bus = axi.AXIInterface(data_width=data_width, address_width=33, id_width=8) # self.platform.add_extension(_debug_io) # debug_io = platform.request("debug_io") @@ -368,87 +368,87 @@ def generate(root, namespaces): axi_target0 = et.SubElement(ddr, "efxpt:axi_target0",is_axi_width_256="false", is_axi_enable="true") gen_pin_target0 = et.SubElement(axi_target0, "efxpt:gen_pin_axi") et.SubElement(gen_pin_target0, "efxpt:pin", name=axi_clk, type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_apcmd", type_name="ARAPCMD_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_ready", type_name="ARREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_valid", type_name="ARVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_qos", type_name="ARQOS_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_apcmd", type_name="AWAPCMD_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_allstrb", type_name="AWALLSTRB_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arapcmd", type_name="ARAPCMD_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arready", type_name="ARREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arvalid", type_name="ARVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arqos", type_name="ARQOS_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awapcmd", type_name="AWAPCMD_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awallstrb", type_name="AWALLSTRB_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awcobuf", type_name="AWCOBUF_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_ready", type_name="AWREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_valid", type_name="AWVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_lock", type_name="AWLOCK_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_qos", type_name="AWQOS_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_ready", type_name="BREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_valid", type_name="BVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_last", type_name="RLAST_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_ready", type_name="RREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_valid", type_name="RVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_last", type_name="WLAST_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_ready", type_name="WREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_valid", type_name="WVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_addr", type_name="ARADDR_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_burst", type_name="ARBURST_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_id", type_name="ARID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_len", type_name="ARLEN_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_size", type_name="ARSIZE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_lock", type_name="ARLOCK_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_addr", type_name="AWADDR_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_burst", type_name="AWBURST_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_id", type_name="AWID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_len", type_name="AWLEN_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_size", type_name="AWSIZE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_cache", type_name="AWCACHE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_id", type_name="BID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_resp", type_name="BRESP_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_data", type_name="RDATA_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_id", type_name="RID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_resp", type_name="RRESP_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_data", type_name="WDATA_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_strb", type_name="WSTRB_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awready", type_name="AWREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awvalid", type_name="AWVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awlock", type_name="AWLOCK_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awqos", type_name="AWQOS_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bready", type_name="BREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bvalid", type_name="BVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rlast", type_name="RLAST_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rready", type_name="RREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rvalid", type_name="RVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wlast", type_name="WLAST_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wready", type_name="WREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wvalid", type_name="WVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_araddr", type_name="ARADDR_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arburst", type_name="ARBURST_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arid", type_name="ARID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arlen", type_name="ARLEN_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arsize", type_name="ARSIZE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arlock", type_name="ARLOCK_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awaddr", type_name="AWADDR_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awburst", type_name="AWBURST_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awid", type_name="AWID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awlen", type_name="AWLEN_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awsize", type_name="AWSIZE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awcache", type_name="AWCACHE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bid", type_name="BID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bresp", type_name="BRESP_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rdata", type_name="RDATA_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rid", type_name="RID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rresp", type_name="RRESP_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wdata", type_name="WDATA_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wstrb", type_name="WSTRB_0", is_bus="true") et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_resetn", type_name="ARSTN_0", is_bus="false") axi_target1 = et.SubElement(ddr, "efxpt:axi_target1",is_axi_width_256="false", is_axi_enable="false") gen_pin_target1 = et.SubElement(axi_target1, "efxpt:gen_pin_axi") et.SubElement(gen_pin_target1, "efxpt:pin", name=axi_clk, type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_apcmd", type_name="ARAPCMD_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_ready", type_name="ARREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_valid", type_name="ARVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_qos", type_name="ARQOS_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_apcmd", type_name="AWAPCMD_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_allstrb", type_name="AWALLSTRB_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arapcmd", type_name="ARAPCMD_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arready", type_name="ARREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arvalid", type_name="ARVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arqos", type_name="ARQOS_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awapcmd", type_name="AWAPCMD_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awallstrb", type_name="AWALLSTRB_1", is_bus="false") et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awcobuf", type_name="AWCOBUF_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_ready", type_name="AWREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_valid", type_name="AWVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_lock", type_name="AWLOCK_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_qos", type_name="AWQOS_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_b_ready", type_name="BREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_b_valid", type_name="BVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_r_last", type_name="RLAST_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_r_ready", type_name="RREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_r_valid", type_name="RVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_w_last", type_name="WLAST_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_w_ready", type_name="WREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_w_valid", type_name="WVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_addr", type_name="ARADDR_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_burst", type_name="ARBURST_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_id", type_name="ARID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_len", type_name="ARLEN_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_size", type_name="ARSIZE_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_ar_lock", type_name="ARLOCK_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_addr", type_name="AWADDR_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_burst", type_name="AWBURST_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_id", type_name="AWID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_len", type_name="AWLEN_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_size", type_name="AWSIZE_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_aw_cache", type_name="AWCACHE_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_b_id", type_name="BID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_b_resp", type_name="BRESP_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_r_data", type_name="RDATA_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_r_id", type_name="RID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_r_resp", type_name="RRESP_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_w_data", type_name="WDATA_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_w_strb", type_name="WSTRB_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awready", type_name="AWREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awvalid", type_name="AWVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awlock", type_name="AWLOCK_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awqos", type_name="AWQOS_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bready", type_name="BREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bvalid", type_name="BVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rlast", type_name="RLAST_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rready", type_name="RREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rvalid", type_name="RVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wlast", type_name="WLAST_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wready", type_name="WREADY_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wvalid", type_name="WVALID_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_araddr", type_name="ARADDR_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arburst", type_name="ARBURST_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arid", type_name="ARID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arlen", type_name="ARLEN_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arsize", type_name="ARSIZE_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arlock", type_name="ARLOCK_1", is_bus="false") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awaddr", type_name="AWADDR_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awburst", type_name="AWBURST_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awid", type_name="AWID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awlen", type_name="AWLEN_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awsize", type_name="AWSIZE_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awcache", type_name="AWCACHE_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bid", type_name="BID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bresp", type_name="BRESP_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rdata", type_name="RDATA_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rid", type_name="RID_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rresp", type_name="RRESP_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wdata", type_name="WDATA_1", is_bus="true") + et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wstrb", type_name="WSTRB_1", is_bus="true") et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_resetn", type_name="ARSTN_1", is_bus="false") gen_pin_controller = et.SubElement(ddr, "efxpt:gen_pin_controller") @@ -607,88 +607,23 @@ def generate(root, namespaces): # DRAM AXI-Ports. # -------------- + axi_io = platform.add_iface_ios(axi_bus.get_ios("ddr0")) + self.comb += axi_bus.connect_to_pads(axi_io, mode="master") + ios = [(f"ddr0", 0, - Subsignal("ar_valid", Pins(1)), - Subsignal("ar_ready", Pins(1)), - Subsignal("ar_addr", Pins(33)), - Subsignal("ar_id", Pins(6)), - Subsignal("ar_len", Pins(8)), - Subsignal("ar_size", Pins(3)), - Subsignal("ar_burst", Pins(2)), - Subsignal("ar_lock", Pins(1)), - Subsignal("ar_apcmd", Pins(1)), - Subsignal("ar_qos", Pins(1)), - Subsignal("aw_valid", Pins(1)), - Subsignal("aw_ready", Pins(1)), - Subsignal("aw_addr", Pins(33)), - Subsignal("aw_id", Pins(6)), - Subsignal("aw_len", Pins(8)), - Subsignal("aw_size", Pins(3)), - Subsignal("aw_burst", Pins(2)), - Subsignal("aw_lock", Pins(1)), - Subsignal("aw_cache", Pins(4)), - Subsignal("aw_qos", Pins(1)), - Subsignal("aw_allstrb", Pins(1)), - Subsignal("aw_apcmd", Pins(1)), + Subsignal("arapcmd", Pins(1)), + Subsignal("awallstrb", Pins(1)), + Subsignal("awapcmd", Pins(1)), Subsignal("awcobuf", Pins(1)), - Subsignal("w_valid", Pins(1)), - Subsignal("w_ready", Pins(1)), - Subsignal("w_data", Pins(data_width)), - Subsignal("w_strb", Pins(data_width//8)), - Subsignal("w_last", Pins(1)), - Subsignal("b_valid", Pins(1)), - Subsignal("b_ready", Pins(1)), - Subsignal("b_resp", Pins(1)), - Subsignal("b_id", Pins(6)), - Subsignal("r_valid", Pins(1)), - Subsignal("r_ready", Pins(1)), - Subsignal("r_data", Pins(data_width)), - Subsignal("r_id", Pins(6)), - Subsignal("r_resp", Pins(2)), - Subsignal("r_last", Pins(1)), Subsignal("resetn", Pins(1)), )] io = platform.add_iface_ios(ios) self.comb += [ - io.ar_valid.eq(axi_bus.ar.valid), - axi_bus.ar.ready.eq(io.ar_ready), - io.ar_addr.eq(axi_bus.ar.addr), - io.ar_id.eq(axi_bus.ar.id), - io.ar_len.eq(axi_bus.ar.len), - io.ar_size.eq(axi_bus.ar.size), - io.ar_burst.eq(axi_bus.ar.burst), - io.ar_lock.eq(axi_bus.ar.lock), - io.ar_apcmd.eq(0), - io.ar_qos.eq(axi_bus.ar.qos), - io.aw_valid.eq(axi_bus.aw.valid), - axi_bus.aw.ready.eq(io.aw_ready), - io.aw_addr.eq(axi_bus.aw.addr), - io.aw_id.eq(axi_bus.aw.id), - io.aw_len.eq(axi_bus.aw.len), - io.aw_size.eq(axi_bus.aw.size), - io.aw_burst.eq(axi_bus.aw.burst), - io.aw_lock.eq(axi_bus.aw.lock), - io.aw_cache.eq(axi_bus.aw.cache), - io.aw_qos.eq(axi_bus.aw.qos), - io.aw_allstrb.eq(0 if not hasattr(self.cpu, "mBus_awallStrb") else self.cpu.mBus_awallStrb), - io.aw_apcmd.eq(0), + io.arapcmd.eq(0), + io.awallstrb.eq(0 if not hasattr(self.cpu, "mBus_awallStrb") else self.cpu.mBus_awallStrb), + io.awapcmd.eq(0), io.awcobuf.eq(0), - io.w_valid.eq(axi_bus.w.valid), - axi_bus.w.ready.eq(io.w_ready), - io.w_data.eq(axi_bus.w.data), - io.w_strb.eq(axi_bus.w.strb), - io.w_last.eq(axi_bus.w.last), - axi_bus.b.valid.eq(io.b_valid), - io.b_ready.eq(axi_bus.b.ready), - axi_bus.b.resp.eq(io.b_resp), - axi_bus.b.id.eq(io.b_id), - axi_bus.r.valid.eq(io.r_valid), - io.r_ready.eq(axi_bus.r.ready), - axi_bus.r.data.eq(io.r_data), - axi_bus.r.id.eq(io.r_id), - axi_bus.r.resp.eq(io.r_resp), - axi_bus.r.last.eq(io.r_last), io.resetn.eq(~self.crg.cd_sys.rst), ] From 715dfe7178eaba21df50b32837409fa1749ff372 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 22 Jan 2025 15:25:18 +0100 Subject: [PATCH 3/3] targets: efinix_ti375_c529_dev_kit: use python api for DDR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use the efinix python api for the DRAM Block. Signed-off-by: Fin Maaß --- .../targets/efinix_ti375_c529_dev_kit.py | 392 ++++++------------ 1 file changed, 134 insertions(+), 258 deletions(-) diff --git a/litex_boards/targets/efinix_ti375_c529_dev_kit.py b/litex_boards/targets/efinix_ti375_c529_dev_kit.py index 3d1713024..4063d04b1 100755 --- a/litex_boards/targets/efinix_ti375_c529_dev_kit.py +++ b/litex_boards/targets/efinix_ti375_c529_dev_kit.py @@ -329,10 +329,9 @@ def __init__(self, # LPDDR4 SDRAM ----------------------------------------------------------------------------- if not self.integrated_main_ram_size: - # DRAM / PLL Blocks. + # DRAM Blocks. # ------------------ - from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock - import xml.etree.ElementTree as et + from litex.build.efinix import InterfaceWriterBlock data_width = 512 axi_bus = axi.AXIInterface(data_width=data_width, address_width=33, id_width=8) @@ -348,262 +347,139 @@ def __init__(self, # self.sync += debug_io.p6.eq(axi_bus.aw.ready) # self.sync += debug_io.p7.eq(axi_bus.b.ready) - axi_clk = self.crg.cd_cpu.clk.name_override - class DRAMXMLBlock(InterfaceWriterXMLBlock): + if hasattr(self.cpu, "add_memory_buses") and hasattr(self.cpu, "cpu_clk"): + axi_clk = self.crg.cd_cpu.clk.name_override + else: + axi_clk = self.crg.cd_sys.clk.name_override + + class EfinixDRAMBlock(InterfaceWriterBlock): @staticmethod - def generate(root, namespaces): - # CHECKME: Switch to DDRDesignService? - ddr_info = root.find("efxpt:ddr_info", namespaces) - - ddr = et.SubElement(ddr_info, "efxpt:adv_ddr", - name = "ddr_inst1", - ddr_def = "DDR_0", - clkin_sel = "0", - data_width = "32", - physical_rank = "1", - mem_type = "LPDDR4x", - mem_density = "8G", - ) - - axi_target0 = et.SubElement(ddr, "efxpt:axi_target0",is_axi_width_256="false", is_axi_enable="true") - gen_pin_target0 = et.SubElement(axi_target0, "efxpt:gen_pin_axi") - et.SubElement(gen_pin_target0, "efxpt:pin", name=axi_clk, type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arapcmd", type_name="ARAPCMD_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arready", type_name="ARREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arvalid", type_name="ARVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arqos", type_name="ARQOS_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awapcmd", type_name="AWAPCMD_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awallstrb", type_name="AWALLSTRB_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awcobuf", type_name="AWCOBUF_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awready", type_name="AWREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awvalid", type_name="AWVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awlock", type_name="AWLOCK_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awqos", type_name="AWQOS_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bready", type_name="BREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bvalid", type_name="BVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rlast", type_name="RLAST_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rready", type_name="RREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rvalid", type_name="RVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wlast", type_name="WLAST_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wready", type_name="WREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wvalid", type_name="WVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_araddr", type_name="ARADDR_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arburst", type_name="ARBURST_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arid", type_name="ARID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arlen", type_name="ARLEN_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arsize", type_name="ARSIZE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_arlock", type_name="ARLOCK_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awaddr", type_name="AWADDR_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awburst", type_name="AWBURST_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awid", type_name="AWID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awlen", type_name="AWLEN_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awsize", type_name="AWSIZE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awcache", type_name="AWCACHE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bid", type_name="BID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_bresp", type_name="BRESP_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rdata", type_name="RDATA_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rid", type_name="RID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_rresp", type_name="RRESP_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wdata", type_name="WDATA_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_wstrb", type_name="WSTRB_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_resetn", type_name="ARSTN_0", is_bus="false") - - axi_target1 = et.SubElement(ddr, "efxpt:axi_target1",is_axi_width_256="false", is_axi_enable="false") - gen_pin_target1 = et.SubElement(axi_target1, "efxpt:gen_pin_axi") - et.SubElement(gen_pin_target1, "efxpt:pin", name=axi_clk, type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arapcmd", type_name="ARAPCMD_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arready", type_name="ARREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arvalid", type_name="ARVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arqos", type_name="ARQOS_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awapcmd", type_name="AWAPCMD_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awallstrb", type_name="AWALLSTRB_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awcobuf", type_name="AWCOBUF_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awready", type_name="AWREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awvalid", type_name="AWVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awlock", type_name="AWLOCK_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awqos", type_name="AWQOS_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bready", type_name="BREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bvalid", type_name="BVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rlast", type_name="RLAST_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rready", type_name="RREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rvalid", type_name="RVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wlast", type_name="WLAST_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wready", type_name="WREADY_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wvalid", type_name="WVALID_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_araddr", type_name="ARADDR_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arburst", type_name="ARBURST_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arid", type_name="ARID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arlen", type_name="ARLEN_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arsize", type_name="ARSIZE_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_arlock", type_name="ARLOCK_1", is_bus="false") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awaddr", type_name="AWADDR_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awburst", type_name="AWBURST_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awid", type_name="AWID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awlen", type_name="AWLEN_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awsize", type_name="AWSIZE_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_awcache", type_name="AWCACHE_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bid", type_name="BID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_bresp", type_name="BRESP_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rdata", type_name="RDATA_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rid", type_name="RID_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_rresp", type_name="RRESP_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wdata", type_name="WDATA_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_wstrb", type_name="WSTRB_1", is_bus="true") - et.SubElement(gen_pin_target1, "efxpt:pin", name="ddr1_resetn", type_name="ARSTN_1", is_bus="false") - - gen_pin_controller = et.SubElement(ddr, "efxpt:gen_pin_controller") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CLK", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_INT", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_MEM_RST_VALID", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_REFRESH", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_BUSY", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CMD_Q_ALMOST_FULL", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_DP_IDLE", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CKE", is_bus="true") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_PORT_BUSY", is_bus="true") - - gen_pin_cfg_ctrl = et.SubElement(ddr, "efxpt:gen_pin_cfg_ctrl") - et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_done", type_name="CFG_DONE", is_bus="false") - et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_start", type_name="CFG_START", is_bus="false") - et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_reset", type_name="CFG_RESET", is_bus="false") - et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_sel", type_name="CFG_SEL", is_bus="false") - - ctrl_reg_inf = et.SubElement(ddr, "efxpt:ctrl_reg_inf", is_reg_ena= "false") - gen_pin_ctrl_reg_inf = et.SubElement(ctrl_reg_inf, "efxpt:gen_pin_ctrl_reg_inf") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="axi0_ACLK", type_name="CR_ACLK", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARESETn", type_name="CR_ARESETN", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARVALID", type_name="CR_ARVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARREADY", type_name="CR_ARREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWVALID", type_name="CR_AWVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWREADY", type_name="CR_AWREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBVALID", type_name="CR_BVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBREADY", type_name="CR_BREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRLAST", type_name="CR_RLAST", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRVALID", type_name="CR_RVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRREADY", type_name="CR_RREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWLAST", type_name="CR_WLAST", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWVALID", type_name="CR_WVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWREADY", type_name="CR_WREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARADDR", type_name="CR_ARADDR", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARID", type_name="CR_ARID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARLEN", type_name="CR_ARLEN", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARSIZE", type_name="CR_ARSIZE", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARBURST", type_name="CR_ARBURST", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWADDR", type_name="CR_AWADDR", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWID", type_name="CR_AWID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWLEN", type_name="CR_AWLEN", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWSIZE", type_name="CR_AWSIZE", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWBURST", type_name="CR_AWBURST", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBID", type_name="CR_BID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBRESP", type_name="CR_BRESP", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRDATA", type_name="CR_RDATA", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRID", type_name="CR_RID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRRESP", type_name="CR_RRESP", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWDATA", type_name="CR_WDATA", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWSTRB", type_name="CR_WSTRB", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="" , type_name="CFG_PHY_RSTN", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="" , type_name="CTRL_RSTN", is_bus="false") - - cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLDOWN_DRV", value="34.3", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLDOWN_ODT", value="60", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLUP_DRV", value="34.3", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLUP_ODT", value="Hi-Z", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="FPGA_VREF_RANGE0", value="22.040", value_type="float") - et.SubElement(cs_fpga,"efxpt:param", name="FPGA_VREF_RANGE1", value="23.000", value_type="float") - et.SubElement(cs_fpga,"efxpt:param", name="MEM_FPGA_VREF_RANGE", value="Range 1", value_type="str") - - cs_memory = et.SubElement(ddr, "efxpt:cs_memory") - et.SubElement(cs_memory,"efxpt:param", name="BLEN", value="BL=16 Sequential", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="CA_ODT_CS0", value="RZQ/4", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="CA_ODT_CS1", value="Disable", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="CA_VREF_RANGE0", value="27.200", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="CA_VREF_RANGE1", value="22.000", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="DQ_ODT_CS0", value="RZQ/4", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="DQ_ODT_CS1", value="Disable", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="DQ_VREF_RANGE0", value="20.000", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="DQ_VREF_RANGE1", value="27.200", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="MEM_CA_RANGE", value="RANGE[1]", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="MEM_DQ_RANGE", value="RANGE[1]", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="NWR", value="nWR=6", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTD_CA_CS0", value="Obeys ODT_CA Bond Pad", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTD_CA_CS1", value="Obeys ODT_CA Bond Pad", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CK_CS0", value="Override Disabled", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CK_CS1", value="Override Disabled", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CS_CS0", value="Override Disabled", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CS_CS1", value="Override Disabled", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="PDDS_CS0", value="RZQ/6", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="PDDS_CS1", value="RFU", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ", value="Yes", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ_DISABLED", value="RL=6,nRTP=8", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ_ENABLED", value="RL=6,nRTP=8", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_WRITE", value="Yes", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="WL_SET", value="Set A", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="WL_SET_A", value="WL=4", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="WL_SET_B", value="WL=4", value_type="str") - - cs_memory_timing = et.SubElement(ddr, "efxpt:cs_memory_timing") - et.SubElement(cs_memory_timing,"efxpt:param", name="tCCD", value="8", value_type="int") - et.SubElement(cs_memory_timing,"efxpt:param", name="tCCDMW", value="32", value_type="int") - et.SubElement(cs_memory_timing,"efxpt:param", name="tFAW", value="40.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tPPD", value="4", value_type="int") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRAS", value="42.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRCD", value="18.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRPab", value="21.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRPpb", value="18.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRRD", value="10.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRTP", value="7.500", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tSR", value="15.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tWR", value="18.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tWTR", value="10.000", value_type="float") - - - pin_swap = et.SubElement(ddr, "efxpt:pin_swap") - et.SubElement(pin_swap,"efxpt:param", name="CA[0]", value="CA[0]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[1]", value="CA[1]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[2]", value="CA[2]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[3]", value="CA[3]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[4]", value="CA[4]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[5]", value="CA[5]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[0]", value="DM[0]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[1]", value="DM[1]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[2]", value="DM[2]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[3]", value="DM[3]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[0]", value="DQ[3]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[10]", value="DQ[12]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[11]", value="DQ[11]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[12]", value="DQ[8]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[13]", value="DQ[10]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[14]", value="DQ[13]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[15]", value="DQ[14]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[16]", value="DQ[22]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[17]", value="DQ[17]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[18]", value="DQ[18]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[19]", value="DQ[19]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[1]", value="DQ[6]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[20]", value="DQ[16]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[21]", value="DQ[20]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[22]", value="DQ[21]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[23]", value="DQ[23]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[24]", value="DQ[29]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[25]", value="DQ[31]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[26]", value="DQ[28]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[27]", value="DQ[30]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[28]", value="DQ[25]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[29]", value="DQ[27]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[2]", value="DQ[4]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[30]", value="DQ[26]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[31]", value="DQ[24]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[3]", value="DQ[5]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[4]", value="DQ[0]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[5]", value="DQ[1]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[6]", value="DQ[7]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[7]", value="DQ[2]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[8]", value="DQ[15]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[9]", value="DQ[9]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="ENABLE_PIN_SWAP", value="true", value_type="bool") - - platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock()) + def generate(): + name = "ddr_inst1" + ddr_def = "DDR_0" + clkin_sel = "CLKIN 0" + data_width = "32" + physical_rank = "1" + mem_type = "LPDDR4x" + mem_density = "8G" + + cmd = [] + cmd.append('design.create_block("{}", "DDR")'.format(name)) + cmd.append('design.set_property("{}", "MEMORY_TYPE", "{}", "DDR")'.format(name, mem_type)) + cmd.append('design.set_property("{}", "DQ_WIDTH", "{}", "DDR")'.format(name, data_width)) + cmd.append('design.set_property("{}", "MEMORY_DENSITY", "{}", "DDR")'.format(name, mem_density)) + cmd.append('design.set_property("{}", "PHYSICAL_RANK", "{}", "DDR")'.format(name, physical_rank)) + cmd.append('design.set_property("{}", "CLKIN_SEL", "{}", "DDR")'.format(name, clkin_sel)) + + cmd.append('design.set_property("{}","TARGET0_EN","1", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TARGET1_EN","0", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","AXI0_ARADDR_BUS","ddr0_araddr", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARAPCMD_PIN","ddr0_arapcmd", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARBURST_BUS","ddr0_arburst", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARID_BUS","ddr0_arid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARLEN_BUS","ddr0_arlen", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARLOCK_PIN","ddr0_arlock", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARQOS_PIN","ddr0_arqos", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARREADY_PIN","ddr0_arready", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARSIZE_BUS","ddr0_arsize", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARSTN_PIN","ddr0_resetn", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_ARVALID_PIN","ddr0_arvalid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWADDR_BUS","ddr0_awaddr", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWALLSTRB_PIN","ddr0_awallstrb", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWAPCMD_PIN","ddr0_awapcmd", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWBURST_BUS","ddr0_awburst", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWCACHE_BUS","ddr0_awcache", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWCOBUF_PIN","ddr0_awcobuf", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWID_BUS","ddr0_awid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWLEN_BUS","ddr0_awlen", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWLOCK_PIN","ddr0_awlock", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWQOS_PIN","ddr0_awqos", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWREADY_PIN","ddr0_awready", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWSIZE_BUS","ddr0_awsize", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_AWVALID_PIN","ddr0_awvalid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_BID_BUS","ddr0_bid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_BREADY_PIN","ddr0_bready", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_BRESP_BUS","ddr0_bresp", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_BVALID_PIN","ddr0_bvalid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_CLK_INPUT_PIN","{}", "DDR")'.format(name, axi_clk)) + cmd.append('design.set_property("{}","AXI0_CLK_INVERT_EN","0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_DATA_WIDTH","512", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_RDATA_BUS","ddr0_rdata", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_RID_BUS","ddr0_rid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_RLAST_PIN","ddr0_rlast", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_RREADY_PIN","ddr0_rready", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_RRESP_BUS","ddr0_rresp", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_RVALID_PIN","ddr0_rvalid", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_WDATA_BUS","ddr0_wdata", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_WLAST_PIN","ddr0_wlast", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_WREADY_PIN","ddr0_wready", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_WSTRB_BUS","ddr0_wstrb", "DDR")'.format(name)) + cmd.append('design.set_property("{}","AXI0_WVALID_PIN","ddr0_wvalid", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","BL","BL=16 Sequential", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CA_ODTD_CS0","Obeys ODT_CA Bond Pad", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CA_ODT_CS0","RZQ/4", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CA_VREF_RANGE","Range[1]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CA_VREF_SETTING","22.0", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","CFG_DONE_PIN","cfg_done", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CFG_RESET_PIN","cfg_reset", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CFG_SEL_PIN","cfg_sel", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CFG_START_PIN","cfg_start", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CK_ODTE_CS0","Override Disabled", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CS_ODTE_CS0","Override Disabled", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","CTRL_BUSY_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_CKE_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_CLK_INVERT_EN","0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_CLK_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_CMD_Q_ALMOST_FULL_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_DP_IDLE_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_INT_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_MEM_RST_VALID_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_PORT_BUSY_PIN","", "DDR")'.format(name)) + cmd.append('design.set_property("{}","CTRL_REFRESH_PIN","", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","DBI_READ_EN","1", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DBI_WRITE_EN","1", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_ODT_CS0","RZQ/4", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_PD_DRV_STRENGTH","34.3", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_PD_ODT","60", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_PU_DRV_STRENGTH","34.3", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_PU_ODT","Hi-Z", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_VREF_RANGE","Range[1]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","DQ_VREF_SETTING","27.2", "DDR")'.format(name)) + cmd.append('design.set_property("{}","PDDS_CS0","RZQ/6", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","PIN_SWIZZLE_CA","CA[0],CA[1],CA[2],CA[3],CA[4],CA[5]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM0","DQ[3],DQ[6],DQ[4],DQ[5],DQ[0],DQ[1],DQ[7],DQ[2],DM[0]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM1","DQ[15],DQ[9],DQ[12],DQ[11],DQ[8],DQ[10],DQ[13],DQ[14],DM[1]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM2","DQ[22],DQ[17],DQ[18],DQ[19],DQ[16],DQ[20],DQ[21],DQ[23],DM[2]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM3","DQ[29],DQ[31],DQ[28],DQ[30],DQ[25],DQ[27],DQ[26],DQ[24],DM[3]", "DDR")'.format(name)) + cmd.append('design.set_property("{}","PIN_SWIZZLE_EN","1", "DDR")'.format(name)) + + cmd.append('design.set_property("{}","TCCD","8", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TCCDMW","32", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TFAW","40.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TPPD","4", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TRAS","42.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TRCD","18.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TRPAB","21.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TRPPB","18.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TRRD","10.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TRTP","7.5", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TSR","15.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TWR","18.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","TWTR","10.0", "DDR")'.format(name)) + cmd.append('design.set_property("{}","VREF_RANGE","Range 1", "DDR")'.format(name)) + cmd.append('design.set_property("{}","VREF_SETTING","23.000", "DDR")'.format(name)) + + cmd.append('design.assign_resource("{}", "{}","DDR")\n'.format(name, ddr_def)) + + return '\n'.join(cmd) + '\n' + + platform.toolchain.ifacewriter.blocks.append(EfinixDRAMBlock()) # DRAM AXI-Ports. # --------------