diff --git a/port/stmicro/stm32/src/chips/all.zig b/port/stmicro/stm32/src/chips/all.zig index 4d958d58..dabfac76 100644 --- a/port/stmicro/stm32/src/chips/all.zig +++ b/port/stmicro/stm32/src/chips/all.zig @@ -316541,10 +316541,36 @@ pub const types = struct { }), /// Comparator configuration register 2. CFGR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// COMP channel 1 enable bit. + EN: u1, + /// Scaler bridge enable. + BRGEN: u1, + /// Voltage scaler enable bit. + SCALEN: u1, + /// COMP channel 1 polarity selection bit. + POLARITY: u1, /// Window comparator mode selection bit. WINMODE: u1, - padding: u27, + reserved6: u1, + /// COMP channel 1 interrupt enable. + ITEN: u1, + reserved8: u1, + /// COMP channel 1 hysteresis selection bits. + HYST: HYST, + reserved12: u2, + /// Power Mode of the COMP channel 1. + PWRMODE: PWRMODE, + reserved16: u2, + /// COMP channel 1 inverting input selection field. + INMSEL: INMSEL, + /// COMP channel 1 non-inverting input selection bit. + INPSEL: INPSEL, + reserved24: u3, + /// COMP channel 1 blanking source selection bits. + BLANKING: BLANKING, + reserved31: u3, + /// Lock bit. + LOCK: u1, }), }; }; @@ -316659,10 +316685,37 @@ pub const types = struct { }), /// Comparator configuration register 2. CFGR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// COMP channel 1 enable bit. + EN: u1, + /// Scaler bridge enable. + BRGEN: u1, + /// Voltage scaler enable bit. + SCALEN: u1, + /// COMP channel 1 polarity selection bit. + POLARITY: u1, /// Window comparator mode selection bit. WINMODE: u1, - padding: u27, + reserved6: u1, + /// COMP channel 1 interrupt enable. + ITEN: u1, + reserved8: u1, + /// COMP channel 1 hysteresis selection bits. + HYST: HYST, + reserved12: u2, + /// Power Mode of the COMP channel 1. + PWRMODE: PWRMODE, + reserved16: u2, + /// COMP channel 1 inverting input selection field. + INMSEL: INMSEL, + reserved20: u1, + /// COMP channel 1 non-inverting input selection bit. + INPSEL: INPSEL, + reserved24: u3, + /// COMP channel 1 blanking source selection bits. + BLANKING: BLANKING, + reserved31: u3, + /// Lock bit. + LOCK: u1, }), }; }; @@ -346741,21 +346794,64 @@ pub const types = struct { pub const NOR_PSRAM = extern struct { /// SRAM/NOR-Flash chip-select control register for bank 1. BCR1: mmio.Mmio(packed struct(u32) { - reserved20: u20, + /// Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. + MBKEN: u1, + /// Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:. + MUXEN: u1, + /// Memory type Defines the type of external memory attached to the corresponding memory bank. + MTYP: MTYP, + /// Memory data bus width Defines the external memory device width, valid for all type of memories. + MWID: MWID, + /// Flash access enable Enables NOR Flash memory access operations. + FACCEN: u1, + reserved8: u1, + /// Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode. + BURSTEN: u1, + /// Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. + WAITPOL: WAITPOL, + reserved11: u1, + /// Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:. + WAITCFG: WAITCFG, + /// Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC. + WREN: u1, + /// Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. + WAITEN: u1, + /// Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). + EXTMOD: u1, + /// Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. + ASYNCWAIT: u1, + /// CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved. + CPSIZE: CPSIZE, + /// Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + CBURSTRW: CBURSTRW, /// Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.). CCLKEN: u1, /// Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. WFDIS: u1, - padding: u10, + /// Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low. + NBLSET: u2, + reserved31: u7, + /// FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. + FMCEN: u1, }), /// SRAM/NOR-Flash chip-select timing register for bank 1. BTR: mmio.Mmio(packed struct(u32) { - reserved20: u20, + /// Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. + ADDSET: u4, + /// Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. + ADDHLD: u4, + /// Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ... + DATAST: u8, + /// Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ... + BUSTURN: u4, /// Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula). CLKDIV: u4, /// (see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don't care. DATLAT: u4, - padding: u4, + /// Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. + ACCMOD: ACCMOD, + /// Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:. + DATAHLD: u2, }), /// SRAM/NOR-Flash chip-select control register for bank 2. BCR: mmio.Mmio(packed struct(u32) { @@ -355090,7 +355186,8 @@ pub const types = struct { reserved144: [28]u8, /// I3C maximum read length register. MAXRLR: mmio.Mmio(packed struct(u32) { - reserved16: u16, + /// maximum data write length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMWL command. Software is notified of a MWL update by the I3C_EVR.MWLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMWL CCC. + ML: u16, /// IBI payload data size, in bytes (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 to set the number of data bytes to be sent to the controller after an IBI request has been acknowledged.This field may be updated by hardware on the reception of SETMRL command (which potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. others: same as 100. IBIP: u3, padding: u13, @@ -360366,118 +360463,11 @@ pub const types = struct { ISR: mmio.Mmio(packed struct(u32) { /// (1/2 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. @"CCIF[0]": u1, - reserved3: u2, - /// (1/2 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - @"CMPOK[0]": u1, - reserved9: u5, - /// (2/2 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - @"CCIF[1]": u1, - reserved12: u2, - /// (1/2 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCOF[0]": u1, - /// (2/2 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCOF[1]": u1, - reserved19: u5, - /// (2/2 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - @"CMPOK[1]": u1, - padding: u12, - }), - /// LPTIM interrupt clear register. - ICR: mmio.Mmio(packed struct(u32) { - /// (1/2 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - @"CCCF[0]": u1, - reserved3: u2, - /// (1/2 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - @"CMPOKCF[0]": u1, - reserved9: u5, - /// (2/2 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - @"CCCF[1]": u1, - reserved12: u2, - /// (1/2 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCOCF[0]": u1, - /// (2/2 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCOCF[1]": u1, - reserved19: u5, - /// (2/2 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - @"CMPOKCF[1]": u1, - padding: u12, - }), - /// LPTIM interrupt enable register. - DIER: mmio.Mmio(packed struct(u32) { - /// (1/2 of CCIE) Capture/compare 1 interrupt enable. - @"CCIE[0]": u1, - reserved3: u2, - /// (1/2 of CMPOKIE) Compare register 1 update OK interrupt enable. - @"CMPOKIE[0]": u1, - reserved9: u5, - /// (2/2 of CCIE) Capture/compare 1 interrupt enable. - @"CCIE[1]": u1, - reserved12: u2, - /// (1/2 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCOIE[0]": u1, - /// (2/2 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCOIE[1]": u1, - reserved16: u2, - /// (1/2 of CCDE) Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCDE[0]": u1, - reserved19: u2, - /// (2/2 of CMPOKIE) Compare register 1 update OK interrupt enable. - @"CMPOKIE[1]": u1, - reserved25: u5, - /// (2/2 of CCDE) Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - @"CCDE[1]": u1, - padding: u6, - }), - reserved20: [8]u8, - /// LPTIM compare register 1. - CCR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. - CCR: u16, - padding: u16, - }), - reserved44: [20]u8, - /// LPTIM capture/compare mode register 1. - CCMR: mmio.Mmio(packed struct(u32) { - /// (1/2 of CCSEL) Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. - @"CCSEL[0]": CCSEL, - /// (1/2 of CCE) Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. - @"CCE[0]": u1, - /// (1/2 of CCP_Input) Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - @"CCP_Input[0]": CCP_Input, - reserved8: u4, - /// (1/2 of ICPSC) Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). - @"ICPSC[0]": Filter, - reserved12: u2, - /// (1/2 of ICF) Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - @"ICF[0]": Filter, - reserved16: u2, - /// (2/2 of CCSEL) Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. - @"CCSEL[1]": CCSEL, - /// (2/2 of CCE) Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. - @"CCE[1]": u1, - /// (2/2 of CCP_Input) Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - @"CCP_Input[1]": CCP_Input, - reserved24: u4, - /// (2/2 of ICPSC) Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). - @"ICPSC[1]": Filter, - reserved28: u2, - /// (2/2 of ICF) Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - @"ICF[1]": Filter, - padding: u2, - }), - }; - - /// Low power timer with Output Compare - pub const LPTIM_BASIC = extern struct { - /// LPTIM interrupt and status register. - ISR: mmio.Mmio(packed struct(u32) { - /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + /// (1/2 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, @@ -360489,20 +360479,30 @@ pub const types = struct { UE: u1, /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. REPOK: u1, - reserved24: u15, + /// (2/2 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[1]": u1, + reserved12: u2, + /// (1/2 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[1]": u1, + reserved19: u5, + /// (2/2 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[1]": u1, + reserved24: u4, /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. DIEROK: u1, padding: u7, }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + /// (1/2 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + /// (1/2 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, @@ -360514,20 +360514,30 @@ pub const types = struct { UECF: u1, /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. REPOKCF: u1, - reserved24: u15, + /// (2/2 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[1]": u1, + reserved12: u2, + /// (1/2 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[0]": u1, + /// (2/2 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[1]": u1, + reserved19: u5, + /// (2/2 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[1]": u1, + reserved24: u4, /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. DIEROKCF: u1, padding: u7, }), /// LPTIM interrupt enable register. DIER: mmio.Mmio(packed struct(u32) { - /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + /// (1/2 of CCIE) Capture/compare 1 interrupt enable. @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + /// (1/2 of CMPOKIE) Compare register 1 update OK interrupt enable. @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, @@ -360539,7 +360549,216 @@ pub const types = struct { UEIE: u1, /// Repetition register update OK interrupt Enable. REPOKIE: u1, - padding: u23, + /// (2/2 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[1]": u1, + reserved12: u2, + /// (1/2 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[0]": u1, + /// (2/2 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[1]": u1, + reserved16: u2, + /// (1/2 of CCDE) Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[0]": u1, + reserved19: u2, + /// (2/2 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[1]": u1, + reserved25: u5, + /// (2/2 of CCDE) Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[1]": u1, + padding: u6, + }), + /// LPTIM configuration register. + CFGR: mmio.Mmio(packed struct(u32) { + /// Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + CKSEL: ClockSource, + /// Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes. + CKPOL: CKPOL, + /// Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + CKFLT: Filter, + reserved6: u1, + /// Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + TRGFLT: Filter, + reserved9: u1, + /// Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + PRESC: PRESC, + reserved13: u1, + /// Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details. + TRIGSEL: u3, + reserved17: u1, + /// Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + TRIGEN: TRIGEN, + /// Timeout enable The TIMOUT bit controls the Timeout feature. + TIMOUT: u1, + /// Waveform shape The WAVE bit controls the output shape. + WAVE: u1, + /// Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to. + WAVPOL: WAVPOL, + /// Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + PRELOAD: u1, + /// counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + COUNTMODE: ClockSource, + /// Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + ENC: u1, + padding: u7, + }), + /// LPTIM control register. + CR: mmio.Mmio(packed struct(u32) { + /// LPTIM enable The ENABLE bit is set and cleared by software. + ENABLE: u1, + /// LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + SNGSTRT: u1, + /// Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + CNTSTRT: u1, + /// Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + COUNTRST: u1, + /// Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + RSTARE: u1, + padding: u27, + }), + /// LPTIM compare register 1. + CCR: mmio.Mmio(packed struct(u32) { + /// Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output. + CCR: u16, + padding: u16, + }), + /// LPTIM autoreload register. + ARR: mmio.Mmio(packed struct(u32) { + /// Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + ARR: u16, + padding: u16, + }), + /// LPTIM counter register. + CNT: mmio.Mmio(packed struct(u32) { + /// Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + CNT: u16, + padding: u16, + }), + reserved36: [4]u8, + /// LPTIM configuration register 2. + CFGR2: mmio.Mmio(packed struct(u32) { + /// (1/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[0]": u2, + reserved4: u2, + /// (2/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[1]": u2, + reserved16: u10, + /// (1/2 of ICSEL) LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + @"ICSEL[0]": u2, + reserved20: u2, + /// (2/2 of ICSEL) LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + @"ICSEL[1]": u2, + padding: u10, + }), + /// LPTIM repetition register. + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition register value REP is the repetition value for the LPTIM. + REP: u8, + padding: u24, + }), + /// LPTIM capture/compare mode register 1. + CCMR: mmio.Mmio(packed struct(u32) { + /// (1/2 of CCSEL) Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + @"CCSEL[0]": CCSEL, + /// (1/2 of CCE) Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + @"CCE[0]": u1, + /// (1/2 of CCP_Input) Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + @"CCP_Input[0]": CCP_Input, + reserved8: u4, + /// (1/2 of ICPSC) Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + @"ICPSC[0]": Filter, + reserved12: u2, + /// (1/2 of ICF) Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + @"ICF[0]": Filter, + reserved16: u2, + /// (2/2 of CCSEL) Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + @"CCSEL[1]": CCSEL, + /// (2/2 of CCE) Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + @"CCE[1]": u1, + /// (2/2 of CCP_Input) Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + @"CCP_Input[1]": CCP_Input, + reserved24: u4, + /// (2/2 of ICPSC) Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + @"ICPSC[1]": Filter, + reserved28: u2, + /// (2/2 of ICF) Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + @"ICF[1]": Filter, + padding: u2, + }), + }; + + /// Low power timer with Output Compare + pub const LPTIM_BASIC = extern struct { + /// LPTIM interrupt and status register. + ISR: mmio.Mmio(packed struct(u32) { + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, + /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + ARRM: u1, + /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + EXTTRIG: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, + /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + ARROK: u1, + /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UP: u1, + /// Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWN: u1, + /// LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + UE: u1, + /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + REPOK: u1, + reserved24: u15, + /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + DIEROK: u1, + padding: u7, + }), + /// LPTIM interrupt clear register. + ICR: mmio.Mmio(packed struct(u32) { + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, + /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + ARRMCF: u1, + /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + EXTTRIGCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, + /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + ARROKCF: u1, + /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPCF: u1, + /// Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNCF: u1, + /// Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + UECF: u1, + /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + REPOKCF: u1, + reserved24: u15, + /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + DIEROKCF: u1, + padding: u7, + }), + /// LPTIM interrupt enable register. + DIER: mmio.Mmio(packed struct(u32) { + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, + /// Autoreload match Interrupt Enable. + ARRMIE: u1, + /// External trigger valid edge Interrupt Enable. + EXTTRIGIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, + /// Autoreload register update OK Interrupt Enable. + ARROKIE: u1, + /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + UPIE: u1, + /// Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. + DOWNIE: u1, + /// Update event interrupt enable. + UEIE: u1, + /// Repetition register update OK interrupt Enable. + REPOKIE: u1, + padding: u23, }), /// LPTIM configuration register. CFGR: mmio.Mmio(packed struct(u32) { @@ -437667,22 +437886,37 @@ pub const types = struct { pub const TIM_1CH = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), reserved12: [8]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable @"CCIE[0]": u1, padding: u30, }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag @"CCIF[0]": u1, reserved9: u7, @@ -437692,7 +437926,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/1 of CCG) Capture/compare x (x=1) generation @"CCG[0]": u1, padding: u30, @@ -437719,7 +437954,23 @@ pub const types = struct { @"CCNP[0]": u1, padding: u28, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1) CCR: [1]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -437733,7 +437984,26 @@ pub const types = struct { /// 2-channel timers pub const TIM_2CH = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved4: u4, @@ -437764,7 +438034,8 @@ pub const types = struct { }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable @"CCIE[0]": u1, /// (2/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable @@ -437776,7 +438047,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/2 of CCIF) Capture/compare x (x=1-2) interrupt flag @"CCIF[0]": u1, /// (2/2 of CCIF) Capture/compare x (x=1-2) interrupt flag @@ -437793,7 +438065,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/2 of CCG) Capture/compare x (x=1-2) generation @"CCG[0]": u1, /// (2/2 of CCG) Capture/compare x (x=1-2) generation @@ -437838,18 +438111,54 @@ pub const types = struct { @"CCNP[1]": u1, padding: u24, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1-2) CCR: [2]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value CCR: u16, padding: u16, }), + reserved80: [20]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, }; /// Basic timers pub const TIM_BASIC = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved4: u4, @@ -437857,18 +438166,106 @@ pub const types = struct { MMS: MMS, padding: u25, }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), }; /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP pub const TIM_BASIC_NO_CR2 = extern struct { - reserved12: [12]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), + reserved12: [8]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Update interrupt enable + UIE: u1, + reserved8: u7, /// Update DMA request enable UDE: u1, padding: u23, }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), }; /// Virtual timer for common part of TIM_BASIC and TIM_1CH @@ -437933,22 +438330,34 @@ pub const types = struct { pub const TIM_GP16 = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, /// Direction DIR: DIR, /// Center-aligned mode selection CMS: CMS, - reserved8: u1, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved3: u3, /// Capture/compare DMA selection CCDS: CCDS, - reserved7: u3, + /// Master mode selection + MMS: MMS, /// TI1 selection TI1S: TI1S, padding: u24, @@ -437974,7 +438383,8 @@ pub const types = struct { }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[0]": u1, /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @@ -437986,7 +438396,9 @@ pub const types = struct { reserved6: u1, /// Trigger interrupt enable TIE: u1, - reserved9: u2, + reserved8: u1, + /// Update DMA request enable + UDE: u1, /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @"CCDE[0]": u1, /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @@ -438002,7 +438414,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[0]": u1, /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @@ -438027,7 +438440,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[0]": u1, /// (2/4 of CCG) Capture/compare x (x=1-4) generation @@ -438089,7 +438503,23 @@ pub const types = struct { @"CCNP[3]": u1, padding: u16, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1-4) CCR: [4]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -438112,6 +438542,8 @@ pub const types = struct { DMAB: u16, padding: u16, }), + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, }; }; @@ -438406,22 +438838,37 @@ pub const types = struct { pub const TIM_1CH = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), reserved12: [8]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable @"CCIE[0]": u1, padding: u30, }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag @"CCIF[0]": u1, reserved9: u7, @@ -438431,7 +438878,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/1 of CCG) Capture/compare x (x=1) generation @"CCG[0]": u1, padding: u30, @@ -438458,7 +438906,23 @@ pub const types = struct { @"CCNP[0]": u1, padding: u28, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1) CCR: [1]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -438479,7 +438943,26 @@ pub const types = struct { /// 1-channel with one complementary output timers pub const TIM_1CH_CMP = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { /// Capture/compare preloaded control @@ -438499,7 +438982,11 @@ pub const types = struct { reserved12: [4]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved5: u5, + /// Update interrupt enable + UIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, + reserved5: u3, /// COM interrupt enable COMIE: u1, reserved7: u1, @@ -438513,17 +439000,28 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved5: u5, + /// Update interrupt flag + UIF: u1, + /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag + @"CCIF[0]": u1, + reserved5: u3, /// COM interrupt flag COMIF: u1, reserved7: u1, /// (1/1 of BIF) Break x (x=1) interrupt flag @"BIF[0]": u1, - padding: u24, + reserved9: u1, + /// (1/1 of CCOF) Capture/Compare x (x=1) overcapture flag + @"CCOF[0]": u1, + padding: u22, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved5: u5, + /// Update generation + UG: u1, + /// (1/1 of CCG) Capture/compare x (x=1) generation + @"CCG[0]": u1, + reserved5: u3, /// Capture/Compare control update generation COMG: u1, reserved7: u1, @@ -438531,22 +439029,58 @@ pub const types = struct { @"BG[0]": u1, padding: u24, }), - reserved32: [8]u8, + /// capture/compare mode register 1 (input mode) + CCMR_Input: [1]mmio.Mmio(packed struct(u32) { + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + padding: u24, + }), + reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - reserved2: u2, + /// (1/1 of CCE) Capture/Compare x (x=1) output enable + @"CCE[0]": u1, + /// (1/1 of CCP) Capture/Compare x (x=1) output Polarity + @"CCP[0]": u1, /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable @"CCNE[0]": u1, - padding: u29, + /// (1/1 of CCNP) Capture/Compare x (x=1) output Polarity + @"CCNP[0]": u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, }), - reserved48: [12]u8, /// repetition counter register RCR: mmio.Mmio(packed struct(u32) { /// Repetition counter value REP: u8, padding: u24, }), - reserved68: [16]u8, + /// capture/compare register x (x=1) + CCR: [1]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved68: [12]u8, /// break and dead-time register BDTR: mmio.Mmio(packed struct(u32) { /// Dead-time generator setup @@ -438584,7 +439118,9 @@ pub const types = struct { DMAB: u16, padding: u16, }), - reserved96: [16]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved96: [12]u8, /// alternate function register 1 AF1: mmio.Mmio(packed struct(u32) { /// TIMx_BKIN input enable @@ -438604,11 +439140,37 @@ pub const types = struct { @"BKCMPP[1]": BKINP, padding: u20, }), + reserved104: [4]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// (1/1 of TISEL) Selects TIM_TIx (x=1) input + @"TISEL[0]": u4, + padding: u28, + }), }; /// 2-channel timers pub const TIM_2CH = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved4: u4, @@ -438622,7 +439184,8 @@ pub const types = struct { SMCR: u32, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable @"CCIE[0]": u1, /// (2/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable @@ -438634,7 +439197,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/2 of CCIF) Capture/compare x (x=1-2) interrupt flag @"CCIF[0]": u1, /// (2/2 of CCIF) Capture/compare x (x=1-2) interrupt flag @@ -438651,7 +439215,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/2 of CCG) Capture/compare x (x=1-2) generation @"CCG[0]": u1, /// (2/2 of CCG) Capture/compare x (x=1-2) generation @@ -438696,14 +439261,33 @@ pub const types = struct { @"CCNP[1]": u1, padding: u24, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1-2) CCR: [2]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value CCR: u16, padding: u16, }), - reserved104: [44]u8, + reserved80: [20]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved104: [20]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input @@ -438717,17 +439301,43 @@ pub const types = struct { /// 2-channel with one complementary output timers pub const TIM_2CH_CMP = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: CCDS, /// Master mode selection MMS: MMS, /// TI1 selection TI1S: TI1S, /// (1/2 of OIS) Output Idle state x (x=1,2) @"OIS[0]": u1, - reserved10: u1, + /// (1/1 of OISN) Output Idle state x (x=1) + @"OISN[0]": u1, /// (2/2 of OIS) Output Idle state x (x=1,2) @"OIS[1]": u1, padding: u21, @@ -438736,10 +439346,22 @@ pub const types = struct { SMCR: u32, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved6: u6, + /// Update interrupt enable + UIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, + reserved5: u3, + /// COM interrupt enable + COMIE: u1, /// Trigger interrupt enable TIE: u1, - reserved13: u6, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// (1/1 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[0]": u1, + reserved13: u3, /// COM DMA request enable COMDE: u1, /// Trigger DMA request enable @@ -438748,15 +439370,20 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/2 of CCIF) Capture/compare x (x=1,2) interrupt flag @"CCIF[0]": u1, /// (2/2 of CCIF) Capture/compare x (x=1,2) interrupt flag @"CCIF[1]": u1, - reserved6: u3, + reserved5: u2, + /// COM interrupt flag + COMIF: u1, /// Trigger interrupt flag TIF: u1, - reserved9: u2, + /// (1/1 of BIF) Break x (x=1) interrupt flag + @"BIF[0]": u1, + reserved9: u1, /// (1/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag @"CCOF[0]": u1, /// (2/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag @@ -438765,15 +439392,20 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/2 of CCG) Capture/compare x (x=1,2) generation @"CCG[0]": u1, /// (2/2 of CCG) Capture/compare x (x=1,2) generation @"CCG[1]": u1, - reserved6: u3, + reserved5: u2, + /// Capture/Compare control update generation + COMG: u1, /// Trigger generation TG: u1, - padding: u25, + /// (1/1 of BG) Break x (x=1) generation + @"BG[0]": u1, + padding: u24, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { @@ -438787,12 +439419,45 @@ pub const types = struct { }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - reserved2: u2, + /// (1/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[0]": u1, + /// (1/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[0]": u1, /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable @"CCNE[0]": u1, - padding: u29, + /// (1/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[0]": u1, + /// (2/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[1]": u1, + /// (2/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[1]": u1, + padding: u24, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, }), - reserved52: [16]u8, /// capture/compare register x (x=1-2) CCR: [2]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -438822,7 +439487,44 @@ pub const types = struct { @"BKF[0]": FilterValue, padding: u12, }), - reserved104: [32]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved96: [12]u8, + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + /// TIMx_BKIN input enable + BKINE: u1, + /// (1/2 of BKCMPE) TIM_BRK_CMPx (x=1-2) enable + @"BKCMPE[0]": u1, + /// (2/2 of BKCMPE) TIM_BRK_CMPx (x=1-2) enable + @"BKCMPE[1]": u1, + reserved8: u5, + /// BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) + BKDF1BKE: u1, + /// TIMx_BKIN input polarity + BKINP: BKINP, + /// (1/2 of BKCMPP) TIM_BRK_CMPx (x=1-2) input polarity + @"BKCMPP[0]": BKINP, + /// (2/2 of BKCMPP) TIM_BRK_CMPx (x=1-2) input polarity + @"BKCMPP[1]": BKINP, + padding: u20, + }), + reserved104: [4]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input @@ -438838,19 +439540,40 @@ pub const types = struct { pub const TIM_ADV = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, /// Direction DIR: DIR, /// Center-aligned mode selection CMS: CMS, - reserved8: u1, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: CCDS, + /// Master mode selection + MMS: MMS, + /// TI1 selection + TI1S: TI1S, /// (1/6 of OIS) Output Idle state x (x=1-6) @"OIS[0]": u1, /// (1/4 of OISN) Output Idle state x N x (x=1-4) @@ -438892,7 +439615,8 @@ pub const types = struct { }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[0]": u1, /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @@ -438901,7 +439625,14 @@ pub const types = struct { @"CCIE[2]": u1, /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[3]": u1, - reserved9: u4, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @"CCDE[0]": u1, /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @@ -438910,11 +439641,16 @@ pub const types = struct { @"CCDE[2]": u1, /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @"CCDE[3]": u1, - padding: u19, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[0]": u1, /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @@ -438923,7 +439659,10 @@ pub const types = struct { @"CCIF[2]": u1, /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[3]": u1, - reserved7: u2, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, /// (1/2 of BIF) Break x (x=1,2) interrupt flag @"BIF[0]": u1, /// (2/2 of BIF) Break x (x=1,2) interrupt flag @@ -438947,7 +439686,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[0]": u1, /// (2/4 of CCG) Capture/compare x (x=1-4) generation @@ -438956,7 +439696,10 @@ pub const types = struct { @"CCG[2]": u1, /// (4/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[3]": u1, - reserved7: u2, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, /// (1/2 of BG) Break x (x=1-2) generation @"BG[0]": u1, /// (2/2 of BG) Break x (x=1-2) generation @@ -439023,7 +439766,22 @@ pub const types = struct { @"CCP[5]": u1, padding: u10, }), - reserved48: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), /// repetition counter register RCR: mmio.Mmio(packed struct(u32) { /// Repetition counter value @@ -439038,12 +439796,22 @@ pub const types = struct { }), /// break and dead-time register BDTR: mmio.Mmio(packed struct(u32) { - reserved12: u12, + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: LOCK, + /// Off-state selection for Idle mode + OSSI: OSSI, + /// Off-state selection for Run mode + OSSR: OSSR, /// (1/2 of BKE) Break x (x=1,2) enable @"BKE[0]": u1, /// (1/2 of BKP) Break x (x=1,2) polarity @"BKP[0]": BKP, - reserved16: u2, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, /// (1/2 of BKF) Break x (x=1,2) filter @"BKF[0]": FilterValue, /// (2/2 of BKF) Break x (x=1,2) filter @@ -439054,10 +439822,19 @@ pub const types = struct { @"BKP[1]": BKP, padding: u6, }), - reserved76: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), /// DMA address for full transfer DMAR: u32, - reserved84: [4]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, /// capture/compare mode register 3 CCMR3: mmio.Mmio(packed struct(u32) { reserved2: u2, @@ -439082,7 +439859,9 @@ pub const types = struct { }), /// capture/compare register 5 CCR5: mmio.Mmio(packed struct(u32) { - reserved29: u29, + /// capture/compare x (x=1-4,6) value + CCR: u16, + reserved29: u13, /// (1/3 of GC5C) Group channel 5 and channel x (x=1-3) @"GC5C[0]": GC5C, /// (2/3 of GC5C) Group channel 5 and channel x (x=1-3) @@ -439098,7 +439877,22 @@ pub const types = struct { }), /// alternate function register 1 AF1: mmio.Mmio(packed struct(u32) { - reserved14: u14, + /// TIMx_BKIN input enable + BKINE: u1, + /// (1/2 of BKCMPE) TIM_BRK_CMPx (x=1-2) enable + @"BKCMPE[0]": u1, + /// (2/2 of BKCMPE) TIM_BRK_CMPx (x=1-2) enable + @"BKCMPE[1]": u1, + reserved8: u5, + /// BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) + BKDF1BKE: u1, + /// TIMx_BKIN input polarity + BKINP: BKINP, + /// (1/2 of BKCMPP) TIM_BRK_CMPx (x=1-2) input polarity + @"BKCMPP[0]": BKINP, + /// (2/2 of BKCMPP) TIM_BRK_CMPx (x=1-2) input polarity + @"BKCMPP[1]": BKINP, + reserved14: u2, /// etr_in source selection ETRSEL: u4, padding: u14, @@ -439139,7 +439933,24 @@ pub const types = struct { /// Basic timers pub const TIM_BASIC = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved4: u4, @@ -439147,18 +439958,106 @@ pub const types = struct { MMS: MMS, padding: u25, }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), }; /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP pub const TIM_BASIC_NO_CR2 = extern struct { - reserved12: [12]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), + reserved12: [8]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Update interrupt enable + UIE: u1, + reserved8: u7, /// Update DMA request enable UDE: u1, padding: u23, }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), }; /// Virtual timer for common part of TIM_BASIC and TIM_1CH @@ -439223,22 +440122,34 @@ pub const types = struct { pub const TIM_GP16 = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, /// Direction DIR: DIR, /// Center-aligned mode selection CMS: CMS, - reserved8: u1, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved3: u3, /// Capture/compare DMA selection CCDS: CCDS, - reserved7: u3, + /// Master mode selection + MMS: MMS, /// TI1 selection TI1S: TI1S, padding: u24, @@ -439258,7 +440169,8 @@ pub const types = struct { }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[0]": u1, /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @@ -439270,7 +440182,9 @@ pub const types = struct { reserved6: u1, /// Trigger interrupt enable TIE: u1, - reserved9: u2, + reserved8: u1, + /// Update DMA request enable + UDE: u1, /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @"CCDE[0]": u1, /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @@ -439286,7 +440200,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[0]": u1, /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @@ -439311,7 +440226,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[0]": u1, /// (2/4 of CCG) Capture/compare x (x=1-4) generation @@ -439373,7 +440289,23 @@ pub const types = struct { @"CCNP[3]": u1, padding: u16, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1-4) CCR: [4]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -439396,7 +440328,9 @@ pub const types = struct { DMAB: u16, padding: u16, }), - reserved96: [16]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved96: [12]u8, /// alternate function register 1 AF1: mmio.Mmio(packed struct(u32) { reserved14: u14, @@ -439424,20 +440358,231 @@ pub const types = struct { /// General purpose 32-bit timers pub const TIM_GP32 = extern struct { - reserved36: [36]u8, - /// counter - CNT: u32, - reserved44: [4]u8, - /// auto-reload register - ARR: u32, - reserved52: [4]u8, - /// capture/compare register x (x=1-4) - CCR: [4]u32, - }; - }; - - pub const timer_v2 = struct { - pub const BKBID = enum(u1) { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + /// Direction + DIR: DIR, + /// Center-aligned mode selection + CMS: CMS, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: CCDS, + /// Master mode selection + MMS: MMS, + /// TI1 selection + TI1S: TI1S, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// External trigger filter + ETF: FilterValue, + /// External trigger prescaler + ETPS: ETPS, + /// External clock mode 2 enable + ECE: u1, + /// External trigger polarity + ETP: ETP, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[3]": u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1-2 (input mode) + CCMR_Input: [2]mmio.Mmio(packed struct(u32) { + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// (1/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[0]": u1, + /// (1/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[0]": u1, + reserved3: u1, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[1]": u1, + /// (2/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[2]": u1, + /// (3/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[2]": u1, + reserved11: u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[3]": u1, + /// (4/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[3]": u1, + reserved15: u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + padding: u16, + }), + /// counter + CNT: u32, + /// prescaler + PSC: u32, + /// auto-reload register + ARR: u32, + reserved52: [4]u8, + /// capture/compare register x (x=1-4) + CCR: [4]u32, + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved96: [12]u8, + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// etr_in source selection + ETRSEL: u4, + padding: u14, + }), + reserved104: [4]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// (1/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[1]": u4, + reserved16: u4, + /// (3/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[2]": u4, + reserved24: u4, + /// (4/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[3]": u4, + padding: u4, + }), + }; + }; + + pub const timer_v2 = struct { + pub const BKBID = enum(u1) { /// Break input tim_brk in input mode Input = 0x0, /// Break input tim_brk in bidirectional mode @@ -439863,22 +441008,39 @@ pub const types = struct { pub const TIM_1CH = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, }), reserved12: [8]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable @"CCIE[0]": u1, padding: u30, }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag @"CCIF[0]": u1, reserved9: u7, @@ -439888,7 +441050,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/1 of CCG) Capture/compare x (x=1) generation @"CCG[0]": u1, padding: u30, @@ -439915,7 +441078,23 @@ pub const types = struct { @"CCNP[0]": u1, padding: u28, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1) (Dither mode disabled) CCR: [1]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -439936,7 +441115,28 @@ pub const types = struct { /// 1-channel with one complementary output timers pub const TIM_1CH_CMP = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { /// Capture/compare preloaded control @@ -439956,7 +441156,11 @@ pub const types = struct { reserved12: [4]u8, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved5: u5, + /// Update interrupt enable + UIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, + reserved5: u3, /// COM interrupt enable COMIE: u1, reserved7: u1, @@ -439970,17 +441174,28 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved5: u5, + /// Update interrupt flag + UIF: u1, + /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag + @"CCIF[0]": u1, + reserved5: u3, /// COM interrupt flag COMIF: u1, reserved7: u1, /// (1/1 of BIF) Break x (x=1) interrupt flag @"BIF[0]": u1, - padding: u24, + reserved9: u1, + /// (1/1 of CCOF) Capture/Compare x (x=1) overcapture flag + @"CCOF[0]": u1, + padding: u22, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved5: u5, + /// Update generation + UG: u1, + /// (1/1 of CCG) Capture/compare x (x=1) generation + @"CCG[0]": u1, + reserved5: u3, /// Capture/Compare control update generation COMG: u1, reserved7: u1, @@ -439988,22 +441203,58 @@ pub const types = struct { @"BG[0]": u1, padding: u24, }), - reserved32: [8]u8, + /// capture/compare mode register 1 (input mode) + CCMR_Input: [1]mmio.Mmio(packed struct(u32) { + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + padding: u24, + }), + reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - reserved2: u2, + /// (1/1 of CCE) Capture/Compare x (x=1) output enable + @"CCE[0]": u1, + /// (1/1 of CCP) Capture/Compare x (x=1) output Polarity + @"CCP[0]": u1, /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable @"CCNE[0]": u1, - padding: u29, + /// (1/1 of CCNP) Capture/Compare x (x=1) output Polarity + @"CCNP[0]": u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, }), - reserved48: [12]u8, /// repetition counter register RCR: mmio.Mmio(packed struct(u32) { /// Repetition counter value REP: u8, padding: u24, }), - reserved68: [16]u8, + /// capture/compare register x (x=1) (Dither mode disabled) + CCR: [1]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved68: [12]u8, /// break and dead-time register BDTR: mmio.Mmio(packed struct(u32) { /// Dead-time generator setup @@ -440044,7 +441295,13 @@ pub const types = struct { DTPE: u1, padding: u14, }), - reserved96: [8]u8, + reserved92: [4]u8, + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// (1/1 of TISEL) Selects TIM_TIx (x=1) input + @"TISEL[0]": u4, + padding: u28, + }), /// alternate function register 1 AF1: mmio.Mmio(packed struct(u32) { /// TIMx_BKIN input enable @@ -440084,7 +441341,9 @@ pub const types = struct { OCRSEL: u3, padding: u13, }), - reserved988: [884]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved988: [880]u8, /// DMA control register DCR: mmio.Mmio(packed struct(u32) { /// DMA base address @@ -440103,14 +441362,36 @@ pub const types = struct { /// 2-channel timers pub const TIM_2CH = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), /// control register 2 CR2: u32, /// slave mode control register SMCR: u32, /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable @"CCIE[0]": u1, /// (2/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable @@ -440122,7 +441403,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/2 of CCIF) Capture/compare x (x=1-2) interrupt flag @"CCIF[0]": u1, /// (2/2 of CCIF) Capture/compare x (x=1-2) interrupt flag @@ -440139,7 +441421,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/2 of CCG) Capture/compare x (x=1-2) generation @"CCG[0]": u1, /// (2/2 of CCG) Capture/compare x (x=1-2) generation @@ -440184,7 +441467,23 @@ pub const types = struct { @"CCNP[1]": u1, padding: u24, }), - reserved52: [16]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, /// capture/compare register x (x=1-2) (Dither mode disabled) CCR: [2]mmio.Mmio(packed struct(u32) { /// capture/compare x (x=1-4,6) value @@ -440201,11 +441500,35 @@ pub const types = struct { @"TISEL[1]": u4, padding: u20, }), + reserved104: [8]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, }; /// 2-channel with one complementary output timers pub const TIM_2CH_CMP = extern struct { - reserved4: [4]u8, + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), /// control register 2 CR2: u32, /// slave mode control register @@ -440217,10 +441540,22 @@ pub const types = struct { }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved6: u6, + /// Update interrupt enable + UIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, + reserved5: u3, + /// COM interrupt enable + COMIE: u1, /// Trigger interrupt enable TIE: u1, - reserved13: u6, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// (1/1 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[0]": u1, + reserved13: u3, /// COM DMA request enable COMDE: u1, /// Trigger DMA request enable @@ -440229,15 +441564,20 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/2 of CCIF) Capture/compare x (x=1,2) interrupt flag @"CCIF[0]": u1, /// (2/2 of CCIF) Capture/compare x (x=1,2) interrupt flag @"CCIF[1]": u1, - reserved6: u3, + reserved5: u2, + /// COM interrupt flag + COMIF: u1, /// Trigger interrupt flag TIF: u1, - reserved9: u2, + /// (1/1 of BIF) Break x (x=1) interrupt flag + @"BIF[0]": u1, + reserved9: u1, /// (1/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag @"CCOF[0]": u1, /// (2/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag @@ -440246,15 +441586,20 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/2 of CCG) Capture/compare x (x=1,2) generation @"CCG[0]": u1, /// (2/2 of CCG) Capture/compare x (x=1,2) generation @"CCG[1]": u1, - reserved6: u3, + reserved5: u2, + /// Capture/Compare control update generation + COMG: u1, /// Trigger generation TG: u1, - padding: u25, + /// (1/1 of BG) Break x (x=1) generation + @"BG[0]": u1, + padding: u24, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { @@ -440268,17 +441613,50 @@ pub const types = struct { }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - reserved2: u2, + /// (1/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[0]": u1, + /// (1/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[0]": u1, /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable @"CCNE[0]": u1, - padding: u29, + /// (1/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[0]": u1, + /// (2/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[1]": u1, + /// (2/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[1]": u1, + padding: u24, }), - reserved52: [16]u8, - /// capture/compare register x (x=1-2) - CCR: [2]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register x (x=1-2) + CCR: [2]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, }), reserved68: [8]u8, /// break and dead-time register @@ -440309,7 +441687,19 @@ pub const types = struct { @"BKBID[0]": BKBID, padding: u3, }), - reserved92: [20]u8, + reserved84: [12]u8, + /// break and dead-time register + DTR2: mmio.Mmio(packed struct(u32) { + /// Dead-time falling edge generator setup + DTGF: u8, + reserved16: u8, + /// Deadtime asymmetric enable + DTAE: DTAE, + /// Deadtime preload enable + DTPE: u1, + padding: u14, + }), + reserved92: [4]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input @@ -440319,21 +441709,90 @@ pub const types = struct { @"TISEL[1]": u4, padding: u20, }), + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + /// TIMx_BKIN input enable + BKINE: u1, + /// (1/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[0]": u1, + /// (2/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[1]": u1, + /// (3/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[2]": u1, + /// (4/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[3]": u1, + /// (5/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[4]": u1, + /// (6/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[5]": u1, + /// (7/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[6]": u1, + /// (8/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[7]": u1, + /// TIMx_BKIN input polarity + BKINP: BKINP, + /// (1/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[0]": BKINP, + /// (2/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[1]": BKINP, + /// (3/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[2]": BKINP, + /// (4/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[3]": BKINP, + padding: u18, + }), + /// alternate function register 2 + AF2: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// ocref_clr source selection + OCRSEL: u3, + padding: u13, + }), + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved988: [880]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + reserved16: u3, + /// DMA burst source selection + DBSS: DBSS, + padding: u12, + }), + /// DMA address for full transfer + DMAR: u32, }; /// Advanced Control timers pub const TIM_ADV = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, /// Direction DIR: DIR, /// Center-aligned mode selection CMS: CMS, - reserved8: u1, + /// Auto-reload preload enable + ARPE: u1, /// Clock division CKD: CKD, - padding: u22, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { @@ -440378,14 +441837,17 @@ pub const types = struct { ECE: u1, /// External trigger polarity ETP: ETP, - reserved25: u9, + reserved24: u8, + /// SMS preload enable + SMSPE: u1, /// SMS preload source SMSPS: SMSPS, padding: u6, }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[0]": u1, /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @@ -440394,10 +441856,14 @@ pub const types = struct { @"CCIE[2]": u1, /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[3]": u1, - reserved7: u2, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, /// Break interrupt enable BIE: u1, - reserved9: u1, + /// Update DMA request enable + UDE: u1, /// (1/4 of CCDE) Capture/Compare x (x=1) DMA request enable @"CCDE[0]": u1, /// (2/4 of CCDE) Capture/Compare x (x=1) DMA request enable @@ -440406,7 +441872,11 @@ pub const types = struct { @"CCDE[2]": u1, /// (4/4 of CCDE) Capture/Compare x (x=1) DMA request enable @"CCDE[3]": u1, - reserved20: u7, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + reserved20: u5, /// Index interrupt enable IDXIE: u1, /// Direction change interrupt enable @@ -440419,7 +441889,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[0]": u1, /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @@ -440428,7 +441899,10 @@ pub const types = struct { @"CCIF[2]": u1, /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[3]": u1, - reserved7: u2, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, /// (1/2 of BIF) Break x (x=1,2) interrupt flag @"BIF[0]": u1, /// (2/2 of BIF) Break x (x=1,2) interrupt flag @@ -440461,7 +441935,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[0]": u1, /// (2/4 of CCG) Capture/compare x (x=1-4) generation @@ -440470,7 +441945,10 @@ pub const types = struct { @"CCG[2]": u1, /// (4/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[3]": u1, - reserved7: u2, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, /// (1/2 of BG) Break x (x=1-2) generation @"BG[0]": u1, /// (2/2 of BG) Break x (x=1-2) generation @@ -440538,27 +442016,55 @@ pub const types = struct { @"CCP[5]": u1, padding: u10, }), - reserved48: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), /// repetition counter register RCR: mmio.Mmio(packed struct(u32) { /// Repetition counter value REP: u16, padding: u16, }), - /// capture/compare register x (x=1-4) - CCR: [4]mmio.Mmio(packed struct(u32) { + /// capture/compare register x (x=1-2) (Dither mode enabled) + CCR_DITHER: [2]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + DITHER: u4, /// capture/compare x (x=1-4,6) value CCR: u16, - padding: u16, + padding: u12, }), + reserved68: [8]u8, /// break and dead-time register BDTR: mmio.Mmio(packed struct(u32) { - reserved12: u12, + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: LOCK, + /// Off-state selection for Idle mode + OSSI: OSSI, + /// Off-state selection for Run mode + OSSR: OSSR, /// (1/2 of BKE) Break x (x=1,2) enable @"BKE[0]": u1, /// (1/2 of BKP) Break x (x=1,2) polarity @"BKP[0]": BKP, - reserved16: u2, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, /// (1/2 of BKF) Break x (x=1,2) filter @"BKF[0]": FilterValue, /// (2/2 of BKF) Break x (x=1,2) filter @@ -440579,7 +442085,9 @@ pub const types = struct { }), /// capture/compare register 5 (Dither mode disabled) CCR5: mmio.Mmio(packed struct(u32) { - reserved29: u29, + /// capture/compare x (x=1-4,6) value + CCR: u16, + reserved29: u13, /// (1/3 of GC5C) Group channel 5 and channel x (x=1-3) @"GC5C[0]": GC5C, /// (2/3 of GC5C) Group channel 5 and channel x (x=1-3) @@ -440607,7 +442115,546 @@ pub const types = struct { @"OCPE[1]": u1, padding: u20, }), - reserved88: [4]u8, + /// break and dead-time register + DTR2: mmio.Mmio(packed struct(u32) { + /// Dead-time falling edge generator setup + DTGF: u8, + reserved16: u8, + /// Deadtime asymmetric enable + DTAE: DTAE, + /// Deadtime preload enable + DTPE: u1, + padding: u14, + }), + /// encoder control register + ECR: mmio.Mmio(packed struct(u32) { + /// Index enable + IE: u1, + /// Index direction + IDIR: IDIR, + /// Index blanking + IBLK: IBLK, + /// First index + FIDX: FIDX, + /// Index positioning + IPOS: u2, + reserved16: u8, + /// Pulse width + PW: u8, + /// Pulse width prescaler + PWPRSC: u2, + padding: u6, + }), + /// input selection register + TISEL: mmio.Mmio(packed struct(u32) { + /// (1/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[1]": u4, + reserved16: u4, + /// (3/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[2]": u4, + reserved24: u4, + /// (4/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[3]": u4, + padding: u4, + }), + /// alternate function register 1 + AF1: mmio.Mmio(packed struct(u32) { + /// TIMx_BKIN input enable + BKINE: u1, + /// (1/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[0]": u1, + /// (2/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[1]": u1, + /// (3/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[2]": u1, + /// (4/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[3]": u1, + /// (5/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[4]": u1, + /// (6/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[5]": u1, + /// (7/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[6]": u1, + /// (8/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[7]": u1, + /// TIMx_BKIN input polarity + BKINP: BKINP, + /// (1/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[0]": BKINP, + /// (2/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[1]": BKINP, + /// (3/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[2]": BKINP, + /// (4/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[3]": BKINP, + /// etr_in source selection + ETRSEL: u4, + padding: u14, + }), + /// alternate function register 2 + AF2: mmio.Mmio(packed struct(u32) { + /// TIMx_BKIN2 input enable + BK2INE: u1, + /// (1/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[0]": u1, + /// (2/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[1]": u1, + /// (3/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[2]": u1, + /// (4/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[3]": u1, + /// (5/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[4]": u1, + /// (6/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[5]": u1, + /// (7/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[6]": u1, + /// (8/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[7]": u1, + /// TIMx_BK2IN input polarity + BK2INP: BKINP, + /// (1/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[0]": BKINP, + /// (2/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[1]": BKINP, + /// (3/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[2]": BKINP, + /// (4/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[3]": BKINP, + reserved16: u2, + /// ocref_clr source selection + OCRSEL: u3, + padding: u13, + }), + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved988: [880]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + reserved16: u3, + /// DMA burst source selection + DBSS: DBSS, + padding: u12, + }), + /// DMA address for full transfer + DMAR: u32, + }; + + /// Basic timers + pub const TIM_BASIC = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), + /// control register 2 + CR2: u32, + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP + pub const TIM_BASIC_NO_CR2 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// Virtual timer for common part of TIM_BASIC and TIM_1CH + pub const TIM_CORE = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + padding: u31, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// General purpose 16-bit timers + pub const TIM_GP16 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: URS, + /// One-pulse mode enbaled + OPM: u1, + /// Direction + DIR: DIR, + /// Center-aligned mode selection + CMS: CMS, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: CKD, + reserved11: u1, + /// UIF status bit remapping enable + UIFREMAP: u1, + /// Dithering enable + DITHEN: u1, + padding: u19, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: CCDS, + reserved7: u3, + /// TI1 selection + TI1S: TI1S, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + /// External trigger filter + ETF: FilterValue, + /// External trigger prescaler + ETPS: ETPS, + /// External clock mode 2 enable + ECE: u1, + /// External trigger polarity + ETP: ETP, + reserved24: u8, + /// SMS preload enable + SMSPE: u1, + /// SMS preload source + SMSPS: SMSPS, + padding: u6, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[3]": u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + reserved20: u5, + /// Index interrupt enable + IDXIE: u1, + /// Direction change interrupt enable + DIRIE: u1, + /// Index error interrupt enable + IERRIE: u1, + /// Transition error interrupt enable + TERRIE: u1, + padding: u8, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, + reserved20: u7, + /// Index interrupt flag + IDXIF: u1, + /// Direction change interrupt flag + DIRIF: u1, + /// Index error interrupt flag + IERRIF: u1, + /// Transition error interrupt flag + TERRIF: u1, + padding: u8, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1-2 (input mode) + CCMR_Input: [2]mmio.Mmio(packed struct(u32) { + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// (1/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[0]": u1, + /// (1/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[0]": u1, + reserved3: u1, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[1]": u1, + /// (2/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[2]": u1, + /// (3/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[2]": u1, + reserved11: u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[3]": u1, + /// (4/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[3]": u1, + reserved15: u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register x (x=1-4) (Dither mode disabled) + CCR: [4]mmio.Mmio(packed struct(u32) { + /// capture/compare x (x=1-4,6) value + CCR: u16, + padding: u16, + }), + reserved88: [20]u8, /// encoder control register ECR: mmio.Mmio(packed struct(u32) { /// Index enable @@ -440651,59 +442698,32 @@ pub const types = struct { }), /// alternate function register 2 AF2: mmio.Mmio(packed struct(u32) { - /// TIMx_BKIN2 input enable - BK2INE: u1, - /// (1/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[0]": u1, - /// (2/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[1]": u1, - /// (3/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[2]": u1, - /// (4/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[3]": u1, - /// (5/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[4]": u1, - /// (6/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[5]": u1, - /// (7/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[6]": u1, - /// (8/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable - @"BK2CMPE[7]": u1, - /// TIMx_BK2IN input polarity - BK2INP: BKINP, - /// (1/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity - @"BK2CMPP[0]": BKINP, - /// (2/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity - @"BK2CMPP[1]": BKINP, - /// (3/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity - @"BK2CMPP[2]": BKINP, - /// (4/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity - @"BK2CMPP[3]": BKINP, - padding: u18, + reserved16: u16, + /// ocref_clr source selection + OCRSEL: u3, + padding: u13, }), - }; - - /// Basic timers - pub const TIM_BASIC = extern struct { - reserved4: [4]u8, - /// control register 2 - CR2: u32, - }; - - /// Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP - pub const TIM_BASIC_NO_CR2 = extern struct { - reserved12: [12]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - reserved8: u8, - /// Update DMA request enable - UDE: u1, - padding: u23, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved988: [880]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + reserved16: u3, + /// DMA burst source selection + DBSS: DBSS, + padding: u12, }), + /// DMA address for full transfer + DMAR: u32, }; - /// Virtual timer for common part of TIM_BASIC and TIM_1CH - pub const TIM_CORE = extern struct { + /// General purpose 32-bit timers + pub const TIM_GP32 = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { /// Counter enable @@ -440714,68 +442734,21 @@ pub const types = struct { URS: URS, /// One-pulse mode enbaled OPM: u1, - reserved7: u3, + /// Direction + DIR: DIR, + /// Center-aligned mode selection + CMS: CMS, /// Auto-reload preload enable ARPE: u1, - reserved11: u3, + /// Clock division + CKD: CKD, + reserved11: u1, /// UIF status bit remapping enable UIFREMAP: u1, /// Dithering enable DITHEN: u1, padding: u19, }), - reserved12: [8]u8, - /// DMA/Interrupt enable register - DIER: mmio.Mmio(packed struct(u32) { - /// Update interrupt enable - UIE: u1, - padding: u31, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - /// Update interrupt flag - UIF: u1, - padding: u31, - }), - /// event generation register - EGR: mmio.Mmio(packed struct(u32) { - /// Update generation - UG: u1, - padding: u31, - }), - reserved36: [12]u8, - /// counter - CNT: mmio.Mmio(packed struct(u32) { - /// counter value - CNT: u16, - reserved31: u15, - /// UIF copy - UIFCPY: u1, - }), - /// prescaler - PSC: u32, - /// auto-reload register (Dither mode disabled) - ARR: mmio.Mmio(packed struct(u32) { - /// Auto-reload value - ARR: u16, - padding: u16, - }), - }; - - /// General purpose 16-bit timers - pub const TIM_GP16 = extern struct { - /// control register 1 - CR1: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// Direction - DIR: DIR, - /// Center-aligned mode selection - CMS: CMS, - reserved8: u1, - /// Clock division - CKD: CKD, - padding: u22, - }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved3: u3, @@ -440806,7 +442779,8 @@ pub const types = struct { }), /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt enable + UIE: u1, /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @"CCIE[0]": u1, /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable @@ -440818,7 +442792,9 @@ pub const types = struct { reserved6: u1, /// Trigger interrupt enable TIE: u1, - reserved9: u2, + reserved8: u1, + /// Update DMA request enable + UDE: u1, /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @"CCDE[0]": u1, /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable @@ -440843,7 +442819,8 @@ pub const types = struct { }), /// status register SR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update interrupt flag + UIF: u1, /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @"CCIF[0]": u1, /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag @@ -440877,7 +442854,8 @@ pub const types = struct { }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { - reserved1: u1, + /// Update generation + UG: u1, /// (1/4 of CCG) Capture/compare x (x=1-4) generation @"CCG[0]": u1, /// (2/4 of CCG) Capture/compare x (x=1-4) generation @@ -440939,13 +442917,15 @@ pub const types = struct { @"CCNP[3]": u1, padding: u16, }), - reserved52: [16]u8, + /// counter (Dither mode disabled) + CNT: u32, + /// prescaler + PSC: u32, + /// auto-reload register (Dither mode disabled) + ARR: u32, + reserved52: [4]u8, /// capture/compare register x (x=1-4) (Dither mode disabled) - CCR: [4]mmio.Mmio(packed struct(u32) { - /// capture/compare x (x=1-4,6) value - CCR: u16, - padding: u16, - }), + CCR: [4]u32, reserved88: [20]u8, /// encoder control register ECR: mmio.Mmio(packed struct(u32) { @@ -440995,7 +442975,9 @@ pub const types = struct { OCRSEL: u3, padding: u13, }), - reserved988: [884]u8, + /// Option register 1 Note: Check Reference Manual to parse this register content + OR: u32, + reserved988: [880]u8, /// DMA control register DCR: mmio.Mmio(packed struct(u32) { /// DMA base address @@ -441011,19 +442993,6 @@ pub const types = struct { /// DMA address for full transfer DMAR: u32, }; - - /// General purpose 32-bit timers - pub const TIM_GP32 = extern struct { - reserved36: [36]u8, - /// counter (Dither mode disabled) - CNT: u32, - reserved44: [4]u8, - /// auto-reload register (Dither mode disabled) - ARR: u32, - reserved52: [4]u8, - /// capture/compare register x (x=1-4) (Dither mode disabled) - CCR: [4]u32, - }; }; pub const tsc_v1 = struct { @@ -442599,10 +444568,84 @@ pub const types = struct { /// Universal synchronous asynchronous receiver transmitter pub const USART = extern struct { - reserved16: [16]u8, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: RWU, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: PS, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: WAKE, + /// Word length + M0: M0, + /// USART enable + UE: u1, + padding: u18, + }), /// Control register 2 CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// Line break detection length + LBDL: LBDL, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, /// Last bit clock pulse LBCL: u1, /// Clock phase @@ -442611,16 +444654,30 @@ pub const types = struct { CPOL: CPOL, /// Clock enable CLKEN: u1, - padding: u20, + /// STOP bits + STOP: STOP, + /// LIN mode enable + LINEN: u1, + padding: u17, }), /// Control register 3 CR3: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: IRLP, + /// Half-duplex selection + HDSEL: u1, /// Smartcard NACK enable NACK: u1, /// Smartcard mode enable SCEN: u1, - reserved8: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, /// RTS enable RTSE: u1, /// CTS enable @@ -442825,10 +444882,87 @@ pub const types = struct { /// Universal synchronous asynchronous receiver transmitter pub const USART = extern struct { - reserved16: [16]u8, + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// USARTDIV + BRR: u16, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: RWU, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: PS, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: WAKE, + /// Word length + M0: M0, + /// USART enable + UE: u1, + reserved15: u1, + /// Oversampling mode + OVER8: OVER8, + padding: u16, + }), /// Control register 2 CR2: mmio.Mmio(packed struct(u32) { - reserved8: u8, + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// Line break detection length + LBDL: LBDL, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, /// Last bit clock pulse LBCL: u1, /// Clock phase @@ -442837,16 +444971,30 @@ pub const types = struct { CPOL: CPOL, /// Clock enable CLKEN: u1, - padding: u20, + /// STOP bits + STOP: STOP, + /// LIN mode enable + LINEN: u1, + padding: u17, }), /// Control register 3 CR3: mmio.Mmio(packed struct(u32) { - reserved4: u4, + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: IRLP, + /// Half-duplex selection + HDSEL: u1, /// Smartcard NACK enable NACK: u1, /// Smartcard mode enable SCEN: u1, - reserved8: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, /// RTS enable RTSE: u1, /// CTS enable diff --git a/port/stmicro/stm32/src/generate.zig b/port/stmicro/stm32/src/generate.zig index 62b036cb..425e4e1b 100644 --- a/port/stmicro/stm32/src/generate.zig +++ b/port/stmicro/stm32/src/generate.zig @@ -210,6 +210,11 @@ pub fn main() !void { var registers_dir = try data_dir.openDir("registers", .{ .iterate = true }); defer registers_dir.close(); + //This holds extra data for extended registers + var extends_list_arena = std.heap.ArenaAllocator.init(allocator); + defer extends_list_arena.deinit(); + const extends_list_allocator = extends_list_arena.allocator(); + it = registers_dir.iterate(); while (try it.next()) |entry| { if (entry.kind != .file) @@ -229,11 +234,13 @@ pub fn main() !void { std.log.err("Issue found at {}:{}", .{ diags.getLine(), diags.getColumn() }); } - const register_file = try std.json.parseFromTokenSource(std.json.Value, allocator, &scanner, .{ + var register_file = try std.json.parseFromTokenSource(std.json.Value, allocator, &scanner, .{ .allocate = .alloc_always, }); errdefer register_file.deinit(); + try handle_extends(allocator, extends_list_allocator, ®ister_file.value); + const register_name = try allocator.dupe(u8, entry.name[0 .. entry.name.len - std.fs.path.extension(entry.name).len]); try register_files.put(register_name, register_file); } @@ -620,3 +627,105 @@ fn generate_chips_file( fn chip_file_less_than(_: void, lhs: std.json.Parsed(ChipFile), rhs: std.json.Parsed(ChipFile)) bool { return std.ascii.lessThanIgnoreCase(lhs.value.name, rhs.value.name); } + +// General function to handle inheritance +fn resolve_inheritance_recursively(allocator: std.mem.Allocator, json_data: *std.json.Value, child_full_name: []const u8, accumulator: *std.json.ObjectMap) !void { + const child = json_data.object.get(child_full_name).?; + const list_name = get_section(child_full_name); + + //This element has a parent ! so it needs to be handled. + const extended = child.object.get("extends"); + if (extended) |parent_unqualified_name| { + + //Get access to the parent and its list of items. + const parent = try get_parent(allocator, json_data, child_full_name, parent_unqualified_name.string); + const parent_section_array = parent.value_ptr.object.get(list_name).?.array; + + // If our dictionary doesn't contain an item present in the child add it to the list + for (parent_section_array.items) |parent_element| { + const parent_element_name = if (parent_element.object.get("name")) |name| name.string else @panic("No Name exist in array properties"); + if (!accumulator.contains(parent_element_name)) { + try accumulator.put(parent_element_name, parent_element); + } + } + + if (parent.value_ptr.object.contains("extends")) { + try resolve_inheritance_recursively(allocator, json_data, parent.key_ptr.*, accumulator); + } + } +} + +fn get_parent(allocator: std.mem.Allocator, json_data: *std.json.Value, child_full_name: []const u8, parent_name: []const u8) !std.json.ObjectMap.Entry { + //Get Family name eg Block, Fieldset + var name_iterator = std.mem.splitScalar(u8, child_full_name, '/'); + const family_name = name_iterator.first(); + + //Get qualified parent name + const parent_full_name = try std.fmt.allocPrint(allocator, "{s}/{s}", .{ family_name, parent_name }); + defer allocator.free(parent_full_name); + + return json_data.object.getEntry(parent_full_name).?; +} + +/// In the json data +/// blocks inherit their "items" +/// fieldsets inherit their "feilds" +/// This picks the appropriate item based on its name. +fn get_section(child_full_name: []const u8) []const u8 { + const Item_t = struct { + data_type: []const u8, + section: []const u8, + }; + + const items = [_]Item_t{ + Item_t{ .data_type = "block", .section = "items" }, + Item_t{ .data_type = "fieldset", .section = "fields" }, + }; + + //Get Family name eg Block, Fieldset + var name_iterator = std.mem.splitScalar(u8, child_full_name, '/'); + const family_name = name_iterator.first(); + + inline for (items) |item| { + if (std.mem.eql(u8, item.data_type, family_name)) { + return item.section; + } + } + @panic("Unhandled extends Type"); +} + +/// Reads throught the json data handles the "extends" inheritance. +fn handle_extends(allocator: std.mem.Allocator, extends_allocator: std.mem.Allocator, root_json: *std.json.Value) !void { + var itr = root_json.object.iterator(); + while (itr.next()) |entry| { + const item_name = entry.key_ptr.*; + const item_value = entry.value_ptr; + + if (item_value.*.object.contains("extends")) { + + // This Collects unique items from the ancestors. + var arr: std.json.ObjectMap = std.json.ObjectMap.init(allocator); + defer arr.deinit(); + + // Get child value and kind holder of inherting items + var child = root_json.object.get(item_name).?; + const list_name = get_section(item_name); + + // Add child items to dictionary so they are not overwritten. + for (child.object.get(list_name).?.array.items) |child_item| { + const child_item_name = child_item.object.get("name").?.string; + try arr.put(child_item_name, child_item); + } + + // Handle all parents and grandparents of the current child. + try resolve_inheritance_recursively(allocator, root_json, item_name, &arr); + + // Replacement items will go here and should be released via the arena extends allocator + var new_list = std.json.Array.init(extends_allocator); + for (arr.values()) |value| { + try new_list.append(value); + } + try child.object.put(list_name, std.json.Value{ .array = new_list }); + } + } +}